Help to SImulate Uart TX

I'm using the following code. I've managed to make it work on my fpga before. but when I try to simulate on my modelsim, it seems that it never gets into the statemachine.

I've configured the settings for a 50Mhz clock...also set the config for model sim to be 10ns 10ns for clock high and low.

How should I go about simulating this?

------------------------------------------------------------------------------

--

-- Engineer: Wojciech Powiertowski

--

-- Module Name: transmitter

-- Project Name: UART

-- Description: A VHDL UART controller

--

-- Comments:

-- If your clkFreq or baudRate values are different than you should

-- calculate proper: phase accumulator width and proper tuning word with

-- the following equations:

-- phaseAccWidth = round(log2((clkFreq/(baudRate))^2))

-- phaseAccTuning = round(baudRate*2^(phaseAccWidth+1)/clkFreq)

--

-- Example:

-- clkFreq = 100000000 -- 100MHz

-- baudRate = 115200 -- 115.2kHz

-- phaseAccWidth = 19.5233 -- round it up to 20

-- phaseAccTuning = 2415.9 -- round it up to 2416

--

-- generated baud will have frequency of 115199.99 which is only

-- 0.000005% different than ideal baud rate of 115200

--

------------------------------------------------------------------------------

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity transmitter is port( clk : in std_logic; startTxD : in std_logic; reset : in std_logic; dataTxD : in std_logic_vector (7 downto 0); TxD : out std_logic; showtick : out std_logic; busyTxD : out std_logic ); end transmitter;

architecture TxD_arch of transmitter is -- phase accumulator constants and core - see details on top of the file !!! constant phaseAccWidth : integer := 25; constant phaseAccTuning : integer := 12885; signal phaseAcc : std_logic_vector (phaseAccWidth downto 0);

-- signals in design signal dataBuffer : std_logic_vector (7 downto 0); signal baudTick : std_logic; signal state : integer range 0 to 15; begin

-- baud generator based on phase accumulator baudTickGen : process (clk) is begin if(rising_edge(clk))then phaseAcc