I have built a QPSK modulator, but I have some doubts about the generation of SymbolRate variable.
The SymbolRate range should from 1 to 45 Msymb/s. I intend to use an external AD9850 DDS, which generates the clock from 1 MHz to 45 MHz for clockout the Symbol.
The Symbols (I and Q) is interpolated by x2 or x4.
How can multiply internally this clock (1 to 45 MHz) by x2 or x4 ? I remember that the clock is variable.
It's possible ?
Thansk.
Kappa
Why not run the external DDS at 4Fsym and then *divide* as necessary in the FPGA? Much easier.
-- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Hi Jonathan Bromley,
I could use this system, but should I use a DDS from at least 180 MHz ...
Some other idea ?
Thanks.
Kappa.
Sorry, I should have checked the AD9850 data sheet - it's limited to only 60MHz max output frequency.
You say you need to vary the symbol rate over 1MHz to 45MHz. What size frequency steps?
If you need really smoothly variable frequency, it could be quite tricky...
-- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Hi Jonathan Bromley,
In my application the frequency input of AD9850 is 100MHz, I can safely generate frequencies from 1 to 45 MHz, with step of "100000000 / 2^32" =
0.023283064 Hz.
It is not so difficult, but my problem is to interpolate into the FPGA signal I and Q in order to apply the filter "Baseband Shaping". If I am not mistaken it is necessary to interpolate at least x2 to filter to Nyquist / 2 of SymbolRate.
Example:
SymbolRate 27500000 (Hz) for Iand Q for apply a "Basebad Shaping" at
13750000(Hz) (Nyquist/2) true output SymbolRate is at least 55000000(Hz) (Interpolated by x2 and filter at 13750000 with SRRC Filter).Is there a way to multiply inside a FPGA a variables clock ?
Thanks.
Kappa.
Here's the best solution, although it's also the one requiring the most skilz: You use a constant sample rate. You design a continuously-variable irrational interpolation FIR. This is made possible by using ROMs to sample the impulse response at thousands of locations. Then you use an NCO to adjust the symbol rate to whatever you wish, while keeping the sample rate constant. This makes the design of the post-DAC reconstruction filter easier as well. -Kevin
Hi Kevin Neilson,
I did not understand, you might be more accurate ?
But if I clocking data output (I and Q) as a constant speed, how can have a variable SymbolRate ?
I do not understand.
Kappa.
n
hello i am doing Mtech in VLSI. I am in 3rd sem . i have to implement QPSk in VHDL if your have qpsk modulator in vhdl then pls foreward me
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