synthesis warning

Hi, during synthesis I get many warnings. One of them is :

WARNING:Xst:2404 - FFs/Latches (without init value) have a constant value of 0 in block .

rreg.addr is connected to the input port of a subcell. Is the error in main, or could it also be in the subcell ?

Here is some code (Because of copyright issues is cannot post all of it):

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL;

entity main is port( clk,reset : in std_logic; --btn: in std_logic_vector(2 downto 0); --rx : in std_logic; --tx : out std_logic; --led: out std_logic_vector(7 downto 0); --sseg : out std_logic_vector(7 downto 0); --an : out std_logic_vector(3 downto 0); sw : in std_logic_vector(2 downto 0); -- to/from chip ad : out std_logic_vector(17 downto 0); we_n, oe_n : out std_logic; -- SRAM chip a dio_a : inout std_logic_vector(15 downto 0); ce_a_n,ub_a_n,lb_a_n : out std_logic; -- SRAM chip b dio_b : inout std_logic_vector(15 downto 0); ce_b_n,ub_b_n,lb_b_n : out std_logic;

hsync,vsync : out std_logic; rgb : out std_logic_vector(2 downto 0) ); end main;

architecture Behavioral of main is signal pixel_tick : std_logic; signal wr_tick : std_logic; signal wr_addr : std_logic_vector(17 downto 0); signal wr_data : std_logic_vector(31 downto 0); signal wr_fifo_full : std_logic; signal video_on : std_logic; signal pixel_x,pixel_y : std_logic_vector(9 downto 0); type state_t is (s0,s1); type regs_t is record state : state_t; addr : std_logic_vector(17 downto 0); n : unsigned(2 downto 0); end record; signal rreg,rnext : regs_t; begin vga_pixel_unit : entity vga_pixel_gen port map( clk=>clk,reset=>reset,pixel_tick=>pixel_tick,rgb=>rgb,wr_tick=>wr_tick, wr_addr=>wr_addr,wr_data=>wr_data,wr_fifo_full=>wr_fifo_full,ad=>ad, we_n=>we_n, oe_n=>oe_n,dio_a=>dio_a,ce_a_n=>ce_a_n,ub_a_n=>ub_a_n,lb_a_n=>lb_a_n, dio_b=>dio_b,ce_b_n=>ce_b_n,ub_b_n=>ub_b_n,lb_b_n=>lb_b_n, video_on=>video_on );

vga_sync_unit : entity vga_sync port map( clk=>clk,reset=>reset,hsync=>hsync,vsync=>vsync,video_on=>video_on, p_tick=>pixel_tick, pixel_x=>pixel_x,pixel_y=>pixel_y ); process(clk,reset) begin if reset='1' then rreg.addr '0'); rreg.state

Reply to
Thorsten Kiefer
Loading thread data ...

Here is more code, if it helps.....

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL;

entity vga_pixel_gen is port( clk,reset : in std_logic; pixel_tick : in std_logic; video_on : in std_logic; rgb : out std_logic_vector(2 downto 0); wr_tick : in std_logic; wr_addr : in std_logic_vector(17 downto 0); wr_data : in std_logic_vector(31 downto 0); wr_fifo_full : out std_logic; -- to/from chip ad : out std_logic_vector(17 downto 0); we_n, oe_n : out std_logic; -- SRAM chip a dio_a : inout std_logic_vector(15 downto 0); ce_a_n,ub_a_n,lb_a_n : out std_logic; -- SRAM chip b dio_b : inout std_logic_vector(15 downto 0); ce_b_n,ub_b_n,lb_b_n : out std_logic

); end vga_pixel_gen;

architecture Behavioral of vga_pixel_gen is signal mem,mem_rw,mem_ready : std_logic; signal mem_addr : std_logic_vector(17 downto 0); signal mem_data_f2s,mem_data_s2f : std_logic_vector(31 downto 0); signal s2f_rd,s2f_wr,s2f_full,s2f_empty : std_logic; signal s2f_wdata,s2f_rdata : std_logic_vector(31 downto 0); signal f2sd_rd,f2sd_empty : std_logic; signal f2sd_rdata : std_logic_vector(31 downto 0); signal f2sa_rd,f2sa_empty,f2sa_full : std_logic; signal f2sa_rdata : std_logic_vector(17 downto 0); type state_t is (s10,s20,s30,s40); type regs_t is record state : state_t; addr : std_logic_vector(17 downto 0); end record; signal rreg,rnext : regs_t;

type state2_t is (s210,s220,s230,s240,s250,s260,s270,s280,s290); type regs2_t is record state : state2_t; data : std_logic_vector(31 downto 0); rgb : std_logic_vector(2 downto 0); end record; signal r2reg,r2next : regs2_t; begin s2f_fifo : entity fifo generic map(B => 32,W => 2) port map( clk=>clk,reset=>reset,rd=>s2f_rd,wr=>s2f_wr,w_data=>s2f_wdata, full=>s2f_full,empty=>s2f_empty,r_data=>s2f_rdata ); f2s_data_fifo : entity fifo generic map(B => 32,W => 2) port map( clk=>clk,reset=>reset,rd=>f2sd_rd,wr=>wr_tick,w_data=>wr_data, full=>wr_fifo_full,empty=>f2sd_empty,r_data=>f2sd_rdata ); f2s_addr_fifo : entity fifo generic map(B => 18,W => 2) port map( clk=>clk,reset=>reset,rd=>f2sa_rd,wr=>wr_tick,w_data=>wr_addr, full=>f2sa_full,empty=>f2sa_empty,r_data=>f2sa_rdata ); sram_unit : entity sram_ctrl port map(clk=>clk,reset=>reset,ad=>ad,we_n=>we_n,oe_n=>oe_n,dio_a=>dio_a,ce_a_n=>ce_a_n, ub_a_n=>ub_a_n,lb_a_n=>lb_a_n,dio_b=>dio_b,ce_b_n=>ce_b_n,ub_b_n=>ub_b_n,lb_b_n=>lb_b_n, mem=>mem,rw=>mem_rw,addr=>mem_addr,data_f2s=>mem_data_f2s,data_s2f=>mem_data_s2f,ready=>mem_ready);

process(clk,reset) begin if reset = '1' then rreg.state

Reply to
Thorsten Kiefer

Hi, I solved be removing the type conversions...

REgards Thorsten

Reply to
Thorsten Kiefer

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.