Hi, during synthesis I get many warnings. One of them is :
WARNING:Xst:2404 - FFs/Latches (without init value) have a constant value of 0 in block .
rreg.addr is connected to the input port of a subcell. Is the error in main, or could it also be in the subcell ?
Here is some code (Because of copyright issues is cannot post all of it):
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL;
entity main is port( clk,reset : in std_logic; --btn: in std_logic_vector(2 downto 0); --rx : in std_logic; --tx : out std_logic; --led: out std_logic_vector(7 downto 0); --sseg : out std_logic_vector(7 downto 0); --an : out std_logic_vector(3 downto 0); sw : in std_logic_vector(2 downto 0); -- to/from chip ad : out std_logic_vector(17 downto 0); we_n, oe_n : out std_logic; -- SRAM chip a dio_a : inout std_logic_vector(15 downto 0); ce_a_n,ub_a_n,lb_a_n : out std_logic; -- SRAM chip b dio_b : inout std_logic_vector(15 downto 0); ce_b_n,ub_b_n,lb_b_n : out std_logic;
hsync,vsync : out std_logic; rgb : out std_logic_vector(2 downto 0) ); end main;
architecture Behavioral of main is signal pixel_tick : std_logic; signal wr_tick : std_logic; signal wr_addr : std_logic_vector(17 downto 0); signal wr_data : std_logic_vector(31 downto 0); signal wr_fifo_full : std_logic; signal video_on : std_logic; signal pixel_x,pixel_y : std_logic_vector(9 downto 0); type state_t is (s0,s1); type regs_t is record state : state_t; addr : std_logic_vector(17 downto 0); n : unsigned(2 downto 0); end record; signal rreg,rnext : regs_t; begin vga_pixel_unit : entity vga_pixel_gen port map( clk=>clk,reset=>reset,pixel_tick=>pixel_tick,rgb=>rgb,wr_tick=>wr_tick, wr_addr=>wr_addr,wr_data=>wr_data,wr_fifo_full=>wr_fifo_full,ad=>ad, we_n=>we_n, oe_n=>oe_n,dio_a=>dio_a,ce_a_n=>ce_a_n,ub_a_n=>ub_a_n,lb_a_n=>lb_a_n, dio_b=>dio_b,ce_b_n=>ce_b_n,ub_b_n=>ub_b_n,lb_b_n=>lb_b_n, video_on=>video_on );
vga_sync_unit : entity vga_sync port map( clk=>clk,reset=>reset,hsync=>hsync,vsync=>vsync,video_on=>video_on, p_tick=>pixel_tick, pixel_x=>pixel_x,pixel_y=>pixel_y ); process(clk,reset) begin if reset='1' then rreg.addr '0'); rreg.state