Latest threads in Field-Programmable Gate Arrays

Constraints for router

Hi, I need to ensure that two FFs are placed close to each other. Does anybody know if it's possible? Can I use any cons...

1 18yrs

tiago.bn

1 18yrs tiago.bn

OPB_CENTRAL_DMA

Has anybody used central_dma to copy data between peripherals and processors, or between two buffers in bram mermory. I...

5 18yrs

pbantunez

5 18yrs pbantunez

Have you ever experimented some problem with External Memory?

Hello, I ask for people who has detected some problem in programs running in External Memory (Micron DDR SDRAM). These...

3 18yrs

pbantunez

3 18yrs pbantunez

Processor Debug interface

Hi all, I wanted to know about the different debug interfaces used(or standards present like JTAG etc...) in a wireless...

1 18yrs

vittal.patil

1 18yrs vittal.patil

C problem

hi all, I am using PPC to make runtime configuration to certain luts in EDK , my problem is i created my own C function...

0 18yrs

fatma.abouelella

0 18yrs fatma.abouelella

Insert IP cores

Im trying to make use of the fifo in my Spartan3E starter kit i've added the component declaration and instantiation te...

5 18yrs

me75

5 18yrs me75

Spartan3: INIT_B doesn't go LOW after PROG_B goes LOW in 2% of cases

Hi All, I have a big system which uses more than 1000 Spartan3 FPGAs. The chips are configured either remotely via a de...

2 18yrs

wzab

2 18yrs wzab

synthesis in xilinx

hai, I understood that the design synthesized in one device of xilinx can be implemented in the other device.. but whet...

0 18yrs

rajesh.obli

0 18yrs rajesh.obli

connecting fpga to TI emif

Hi, I have a Lyrtech SFFSDR board, where a virtex4 SX35 is connected to the emif of a davinci dm6446. I woul like to cr...

0 18yrs

nospam

0 18yrs nospam

minipci breadboard with fpga

Hi, I'm looking for a minipci card with an FPGA in order to work for some project. The PCI interface should be programm...

4 18yrs

manuel-lozano

4 18yrs manuel-lozano

Timing Analyzer report for IOBs -- 1GSPS DAC interface

Hi, I'm designing a 1GSPS DAC interface that sends a 500MHz clock and 16bit DDR parallel data in Virtex-5 xc5vlx95t-1ff...

5 18yrs

pato

5 18yrs pato

real time FIR implementation in FPGA

hai, I have stored my filter coefficients in FPGA.I have not stored my input samples it will directly given to the FPGA...

4 18yrs

rajesh.obli

4 18yrs rajesh.obli

VHDL code for RCOM message

Hi, I am presently writing Testcases and Test benches for my Communication control modules which are used in Boeing spo...

3 18yrs

jsreenivas.naidu

3 18yrs jsreenivas.naidu

How do I program an fpga once it has been designed and layout is complete

Trying to design an FPGA from scratch, but not sure how this fpga should be programmed. It is going to be a tile concep...

11 18yrs

phxagent

11 18yrs phxagent

Nintendo DS Screenshots / Video Capture

Hi All, I'm starting to look at building something that will allow me to take screenshots and do video capture of both...

9 18yrs

adwordsmcc

9 18yrs adwordsmcc

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