Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Lattice MachXO2/XO3/XO3D vs ECP5
Can anyone shed some light on why are XO2/3 chips so expenisive compared to ECP5 ? XO2/3 is supposed to be middle-to-low end of their product lines, but simple 6900 LUT XO3 is significantly more...
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4 years ago
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Student seeking for Internship in Digital Design
Respected members, I'm a 3rd-year undergrad, majoring on Electronics & Communication Engineering at IIEST Shibpur, India. I have been experimenting on my Artix-7 Basys-3 board since my 2nd-semester...
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4 years ago
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Here is new definition for keyword "if_2", version 2.
Here is new definition for keyword "if_2", version 2. It is developed based on many discussions after my first post: " New keywor d "if_2" is suggested for dealing with 2-write port memory." New...
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4 years ago
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New keyword "if_2" for HDL is suggested for dealing with 2-write port memory
Hi, In my opinion, using a 2-write port memory is a mature technique and its im plementation in any chip is never a secret. Hardware designers in HDL often use 2-write port memory in their...
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4 years ago
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How to write a correct code to do 2 writes to an array on same cycle?
Hi, Here is a code segment showing 2 methods doing 2 writes to an array with 2 different addresses on the same cycle: 1. p1: process(CLK) is begin if CLK'event and CLK = '1' then if C1 then...
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4 years ago
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[Fully Funded Scholarship] Research Assistantship (Spring, 2020) at the Graduate School, School of Software, Hallym University, Korea
Research Assistantship (Spring, 2020) at the Graduate School, School of Sof tware, Hallym University, Korea The and of the Hallym University seek to recruit promising PhD and MSc or MSc-PhD research...
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4 years ago
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PipelineC (again), dct example, looking for help/interest
Hi folks looking for feedback on PipelineC. Ideas of what to implement next . I will point you to a recent reddit post which ultimately points to GitHub. ower_resource_usage/ Here is the code to get...
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4 years ago
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Re: Philips LA PM3585 disassembler software wanted
Hi, I would be highly interested in the PM3585 disassembler software Regards smed
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4 years ago
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Bayer Pattern to RGB VHDL CODE
Please VHDL Guru's i got 8 rows Bayer signal from MT9 parallel data camera , could someone help me or share VHDL code to convert from Bayer pattern to RGB ?
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4 years ago
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Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking?
Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? I need help to understand a puzzle: Merly-type state machine generates outputs which...
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4 years ago
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VHDL TIME support in Vivado
Y'all. It's 2019. TIME has been in VHDL since what, 1987? And yet Vivado remains unable to successfully divide an amount of time you want to wait by a clock period to get a compile-time integer. is...
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4 years ago
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Lattice XO3D New
It looks like Lattice has announced a new FPGA product that suits my needs. I've always preferred non-BGA devices because they complicate the PCB fab rication with the need for fine pitch and very...
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4 years ago
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New uses of FPGAs
FPGAs are used in a wide variety of applications from automotive to computing and space. Why are they not used inside optical modules?
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4 years ago
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How do big compagnies use Verilog/VHDL for processor designs?
I have a question on how big companies like Intel/AMD use VHDL and Verilog internally for their processors. For example, if they implement an ALU. Do they implement the ALU on an RTL-level or do they...
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4 years ago
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HOW TO READ A 64 BIT REGISTER IN 2 CLOCK CYCLES IN VERILOG
There is a 64bit input that is stored in register. A single clock cycle can read 32bits at a time. For implementing this 4x1 mux is used as 32bit imag e is divided into 8bit. The problem I'm facing is...
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4 years ago
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