Latest threads in Field-Programmable Gate Arrays

Lattice Diamond/LSE Synthesis - implementing ring oscilator in Verilog ?

I can't do it. Every time I try, LSE reports "combinatorial loop" and optimizes whole thing away. I tried using attribu...

6 6yrs

brane331133

6 6yrs brane331133

enum and Vivado

I'm clearly failing to understand how enums are supposed to work in SystemVerilog. I've created a header file with the...

7 6yrs

dab

7 6yrs dab

Looking for MMI M2018 LCA data sheet

Hello, I'm a collector and tinkerer of old, archaic devices, and I recently came across a MMI M2018-20CP (date code 81x...

15 6yrs

please

15 6yrs please

fixed point modeling tools

Hello, For those of you who do DSP modeling in Python, I've recently released a pa ckage that supports fixed point arit...

4 6yrs

zack_sheffield

4 6yrs zack_sheffield

Passing digitized data to design

Hello, Is there a resource that can help me understand how to pass digitized data (from a waveform) to a design that I...

5 6yrs

mohammed.billoo

5 6yrs mohammed.billoo

CFP IEEE International Conference on Computer Design (ICCD) 2020

------------------------------------------------------------------ Call for Papers ------------------------------------...

0 6yrs

sebastien.pillement

0 6yrs sebastien.pillement

Custom CPU Designs

In the Forth language group there are occasional discussions of custom proc essors. This is mostly because a simple sta...

8 6yrs

gnuarm.deletethisbit

8 6yrs gnuarm.deletethisbit

No more gate-level simulation. for Cyclone V !!!

Hello, I'm dealing with some fast state machines and gate-level-timing simulation of some components has been very help...

8 6yrs

cupido

8 6yrs cupido

PipelineC - C-like almost hardware description language - AWS F1 Example

Hi folks, Here to talk about PipelineC. https://github.com/JulianKemmerer/PipelineC/wiki What is it?: - C-like almost h...

2 6yrs

absurdfatalism

2 6yrs absurdfatalism

Using EDA tools at home

Need to use your company EDA tools from home, here are some tips: 1) First of all, the most important solution is to sp...

0 6yrs

henknep4

0 6yrs henknep4

How to generate bits info for a record structure?

Hi, I have a data record designed as follows: type DATA_RECORD_t record I1: unsigned(7 downto 0); I2: unsigned(15 downt...

9 6yrs

wtxwtx

9 6yrs wtxwtx

Code block in icestudio

Hi, I'm trying to program a TinyFPGA BX to provide 3 registers to emulate an FDC9266, the bulk will later be done using...

16 6yrs

josef.moellers

16 6yrs josef.moellers

how to suppress assertion warnings in gtkwave?

hello, is there any way to suppress assertion warnings from std.numeric in gtkwave simulator? thank you

3 6yrs

hex7c3

3 6yrs hex7c3

Apple eBook on Educational CPU design using FPGA

https://books.apple.com/us/book/implementing-a-cpu-using-fpga/id802454238

0 6yrs

othmana

0 6yrs othmana

Displays - Apple Mac vs. IBM PC

I bet the Apple still have a huge leg up on PCs when it comes to displays. Yeah, they both have the same hardware these...

10 6yrs

gnuarm.deletethisbit

10 6yrs gnuarm.deletethisbit

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