Field-Programmable Gate Arrays

enum and Vivado

I'm clearly failing to understand how enums are supposed to work in SystemVerilog. I've created a header file with the...

7 comments posted 6yrs

posted by dab

7 comments posted 6yrs posted by dab

Looking for MMI M2018 LCA data sheet

Hello, I'm a collector and tinkerer of old, archaic devices, and I recently came across a MMI M2018-20CP (date code 81x...

15 comments posted 6yrs

posted by please

15 comments posted 6yrs posted by please

fixed point modeling tools

Hello, For those of you who do DSP modeling in Python, I've recently released a pa ckage that supports fixed point arit...

4 comments posted 6yrs

posted by zack_sheffield

4 comments posted 6yrs posted by zack_sheffield

Passing digitized data to design

Hello, Is there a resource that can help me understand how to pass digitized data (from a waveform) to a design that I...

5 comments posted 6yrs

posted by mohammed.billoo

5 comments posted 6yrs posted by mohammed.billoo

CFP IEEE International Conference on Computer Design (ICCD) 2020

------------------------------------------------------------------ Call for Papers ------------------------------------...

0 comments posted 6yrs

posted by sebastien.pillement

0 comments posted 6yrs posted by sebastien.pillement

Custom CPU Designs

In the Forth language group there are occasional discussions of custom proc essors. This is mostly because a simple sta...

8 comments posted 6yrs

posted by gnuarm.deletethisbit

8 comments posted 6yrs posted by gnuarm.deletethisbit

No more gate-level simulation. for Cyclone V !!!

Hello, I'm dealing with some fast state machines and gate-level-timing simulation of some components has been very help...

8 comments posted 6yrs

posted by cupido

8 comments posted 6yrs posted by cupido

PipelineC - C-like almost hardware description language - AWS F1 Example

Hi folks, Here to talk about PipelineC. https://github.com/JulianKemmerer/PipelineC/wiki What is it?: - C-like almost h...

2 comments posted 6yrs

posted by absurdfatalism

2 comments posted 6yrs posted by absurdfatalism

Using EDA tools at home

Need to use your company EDA tools from home, here are some tips: 1) First of all, the most important solution is to sp...

0 comments posted 6yrs

posted by henknep4

0 comments posted 6yrs posted by henknep4

How to generate bits info for a record structure?

Hi, I have a data record designed as follows: type DATA_RECORD_t record I1: unsigned(7 downto 0); I2: unsigned(15 downt...

9 comments posted 6yrs

posted by wtxwtx

9 comments posted 6yrs posted by wtxwtx

Code block in icestudio

Hi, I'm trying to program a TinyFPGA BX to provide 3 registers to emulate an FDC9266, the bulk will later be done using...

16 comments posted 6yrs

posted by josef.moellers

16 comments posted 6yrs posted by josef.moellers

how to suppress assertion warnings in gtkwave?

hello, is there any way to suppress assertion warnings from std.numeric in gtkwave simulator? thank you

3 comments posted 6yrs

posted by hex7c3

3 comments posted 6yrs posted by hex7c3

Apple eBook on Educational CPU design using FPGA

https://books.apple.com/us/book/implementing-a-cpu-using-fpga/id802454238

0 comments posted 6yrs

posted by othmana

0 comments posted 6yrs posted by othmana

Displays - Apple Mac vs. IBM PC

I bet the Apple still have a huge leg up on PCs when it comes to displays. Yeah, they both have the same hardware these...

10 comments posted 6yrs

posted by gnuarm.deletethisbit

10 comments posted 6yrs posted by gnuarm.deletethisbit

Optimizations, How Much and When?

My projects typically are implemented in small devices and so are often spa ce constrained. So I am in the habit of opt...

11 comments posted 6yrs

posted by gnuarm.deletethisbit

11 comments posted 6yrs posted by gnuarm.deletethisbit