Latest threads in Field-Programmable Gate Arrays

Lattice MachXO2/XO3/XO3D vs ECP5

Can anyone shed some light on why are XO2/3 chips so expenisive compared to ECP5 ? XO2/3 is supposed to be middle-to-lo...

3 6yrs

brankob

3 6yrs brankob

Student seeking for Internship in Digital Design

Respected members, I'm a 3rd-year undergrad, majoring on Electronics & Communication Engineering at IIEST Shibpur, Indi...

0 7yrs

joshuaroy873

0 7yrs joshuaroy873

Here is new definition for keyword "if_2", version 2.

Here is new definition for keyword "if_2", version 2. It is developed based on many discussions after my first post: "...

12 7yrs

wtxwtx

12 7yrs wtxwtx

New keyword "if_2" for HDL is suggested for dealing with 2-write port memory

Hi, In my opinion, using a 2-write port memory is a mature technique and its im plementation in any chip is never a sec...

5 7yrs

wtxwtx

5 7yrs wtxwtx

How to write a correct code to do 2 writes to an array on same cycle?

Hi, Here is a code segment showing 2 methods doing 2 writes to an array with 2 different addresses on the same cycle: 1...

12 7yrs

wtxwtx

12 7yrs wtxwtx

[Fully Funded Scholarship] Research Assistantship (Spring, 2020) at the Graduate School, School of Software, Hallym University, Korea

Research Assistantship (Spring, 2020) at the Graduate School, School of Sof tware, Hallym University, Korea The [Advanc...

0 7yrs

jeonggun.lee

0 7yrs jeonggun.lee

PipelineC (again), dct example, looking for help/interest

Hi folks looking for feedback on PipelineC. Ideas of what to implement next . I will point you to a recent reddit post...

1 7yrs

absurdfatalism

1 7yrs absurdfatalism

Re: Philips LA PM3585 disassembler software wanted

Hi, I would be highly interested in the PM3585 disassembler software Regards smed

1 7yrs

<smed

1 7yrs <smed

Bayer Pattern to RGB VHDL CODE

Please VHDL Guru's i got 8 rows Bayer signal from MT9 parallel data camera , could someone help me or share VHDL code to...

1 7yrs

abirov

1 7yrs abirov

Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking?

Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? I n...

3 7yrs

wtxwtx

3 7yrs wtxwtx

VHDL TIME support in Vivado

Y'all. It's 2019. TIME has been in VHDL since what, 1987? And yet Vivado remains unable to successfully divide an amoun...

12 7yrs

rgaddi

12 7yrs rgaddi

Lattice XO3D New

It looks like Lattice has announced a new FPGA product that suits my needs. I've always preferred non-BGA devices becau...

7 7yrs

gnuarm.deletethisbit

7 7yrs gnuarm.deletethisbit

New uses of FPGAs

FPGAs are used in a wide variety of applications from automotive to computing and space. Why are they not used inside op...

10 7yrs

camil.matiska

10 7yrs camil.matiska

How do big compagnies use Verilog/VHDL for processor designs?

I have a question on how big companies like Intel/AMD use VHDL and Verilog internally for their processors. For example...

2 7yrs

benjamin.couillard

2 7yrs benjamin.couillard

HOW TO READ A 64 BIT REGISTER IN 2 CLOCK CYCLES IN VERILOG

There is a 64bit input that is stored in register. A single clock cycle can read 32bits at a time. For implementing thi...

1 7yrs

bazgha.amin

1 7yrs bazgha.amin

Field-Programmable Gate Arrays

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