Field-Programmable Gate Arrays

Here is new definition for keyword "if_2", version 2.

Here is new definition for keyword "if_2", version 2. It is developed based on many discussions after my first post: "...

12 comments posted 6yrs

posted by wtxwtx

12 comments posted 6yrs posted by wtxwtx

New keyword "if_2" for HDL is suggested for dealing with 2-write port memory

Hi, In my opinion, using a 2-write port memory is a mature technique and its im plementation in any chip is never a sec...

5 comments posted 6yrs

posted by wtxwtx

5 comments posted 6yrs posted by wtxwtx

How to write a correct code to do 2 writes to an array on same cycle?

Hi, Here is a code segment showing 2 methods doing 2 writes to an array with 2 different addresses on the same cycle: 1...

12 comments posted 6yrs

posted by wtxwtx

12 comments posted 6yrs posted by wtxwtx

[Fully Funded Scholarship] Research Assistantship (Spring, 2020) at the Graduate School, School of Software, Hallym University, Korea

Research Assistantship (Spring, 2020) at the Graduate School, School of Sof tware, Hallym University, Korea The [Advanc...

0 comments posted 6yrs

posted by jeonggun.lee

0 comments posted 6yrs posted by jeonggun.lee

PipelineC (again), dct example, looking for help/interest

Hi folks looking for feedback on PipelineC. Ideas of what to implement next . I will point you to a recent reddit post...

1 comments posted 6yrs

posted by absurdfatalism

1 comments posted 6yrs posted by absurdfatalism

Re: Philips LA PM3585 disassembler software wanted

Hi, I would be highly interested in the PM3585 disassembler software Regards smed

1 comments posted 6yrs

posted by <smed

1 comments posted 6yrs posted by <smed

Bayer Pattern to RGB VHDL CODE

Please VHDL Guru's i got 8 rows Bayer signal from MT9 parallel data camera , could someone help me or share VHDL code to...

1 comments posted 6yrs

posted by abirov

1 comments posted 6yrs posted by abirov

Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking?

Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? I n...

3 comments posted 6yrs

posted by wtxwtx

3 comments posted 6yrs posted by wtxwtx

VHDL TIME support in Vivado

Y'all. It's 2019. TIME has been in VHDL since what, 1987? And yet Vivado remains unable to successfully divide an amoun...

12 comments posted 6yrs

posted by rgaddi

12 comments posted 6yrs posted by rgaddi

Lattice XO3D New

It looks like Lattice has announced a new FPGA product that suits my needs. I've always preferred non-BGA devices becau...

7 comments posted 7yrs

posted by gnuarm.deletethisbit

7 comments posted 7yrs posted by gnuarm.deletethisbit

New uses of FPGAs

FPGAs are used in a wide variety of applications from automotive to computing and space. Why are they not used inside op...

10 comments posted 7yrs

posted by camil.matiska

10 comments posted 7yrs posted by camil.matiska

How do big compagnies use Verilog/VHDL for processor designs?

I have a question on how big companies like Intel/AMD use VHDL and Verilog internally for their processors. For example...

2 comments posted 7yrs

posted by benjamin.couillard

2 comments posted 7yrs posted by benjamin.couillard

HOW TO READ A 64 BIT REGISTER IN 2 CLOCK CYCLES IN VERILOG

There is a 64bit input that is stored in register. A single clock cycle can read 32bits at a time. For implementing thi...

1 comments posted 7yrs

posted by bazgha.amin

1 comments posted 7yrs posted by bazgha.amin

Unique uses for the DSP48

I've tried to figure out how to use the Xilinx DSP48s for Galois arithmetic , but they really aren't that useful for th...

8 comments posted 7yrs

posted by kevin.neilson

8 comments posted 7yrs posted by kevin.neilson

Microchip UNI/O controller core for FPGA

Hi, I needed to access the Microchip 11AA02E48 EEPROM located on a FPGA board. Unfortunately, I couldn't find any VHDL/...

0 comments posted 7yrs

posted by wzab01

0 comments posted 7yrs posted by wzab01