How to write a correct code to do 2 writes to an array on same cycle?

Hi,
Here is a code segment showing 2 methods doing 2 writes to an array with 2 different addresses on the same cycle:
1.
p1: process(CLK) is
begin
if CLK'event and CLK = '1' then
if C1 then
An_Array(a)
Reply to
Weng Tianxiang
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2 different addresses on the same cycle:
I think the short answer is YES, the compiler has no way of knowing you are writing to different array elements. More importantly what hardware are y ou expecting this to synthesize? Simulation is one thing, but I don't know this sort of construct is clear enough to produce any particular hardware. Also, are you targeting an FPGA or a custom chip? I expect there to pote ntially be a difference.
Again, the same issue. I believe this code is equivalent to the first exam ple. The assignment statements tend to generate drivers and you may get tw o drivers on the address input to the array. I expect you are intending to generate a dual port RAM with two separate inputs for address and data wit h separate write capability. In FPGAs I use the sample code provided by th e vendor to infer RAMs. Even if I use my own code, I write the RAM code to be an independent module and then instantiate that.
So what is your target?
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  Rick C. 

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Reply to
Rick C
h 2 different addresses on the same cycle:
re writing to different array elements. More importantly what hardware are you expecting this to synthesize? Simulation is one thing, but I don't kn ow this sort of construct is clear enough to produce any particular hardwar e. Also, are you targeting an FPGA or a custom chip? I expect there to po tentially be a difference.
ample. The assignment statements tend to generate drivers and you may get two drivers on the address input to the array. I expect you are intending to generate a dual port RAM with two separate inputs for address and data w ith separate write capability. In FPGAs I use the sample code provided by the vendor to infer RAMs. Even if I use my own code, I write the RAM code to be an independent module and then instantiate that.
Hi Rick,
Thank you for your answer.
Actually I am writing code not targeting any FPGA manufactures, neither Alt era nor Xilinx, I just want that the code can be simulated by Mentor simula tor to prove that my algorithm on a universal subject is working IN THEORY: with 2 write ports for an array, everything is working. By doing so it wil l save me a lot of energy, cost and time.
Translating 2 writes at 2 different addresses for an array in code to a 2 w rite port memory is considered as a mature technology like to implement an 64-bit adder if one decides to select a FPGA chip to implement.
I think based on the definition in a sequential process with or without clo ck, my code is working: if conditions C1 = '1' and C2 = '1', first the simulator by definition executes An_Array(a)
Reply to
Weng Tianxiang
hat my algorithm on a universal subject is working IN THEORY: with 2 write ports for an array, everything is working. By doing so it will save me a lo t of energy, cost and time.
So, you want someone else to run a VHDL simulator for you in order to save you a lot of energy, cost and time? Ummm...why, are you being lazy? I can pretty much guarantee that any VHDL simulator will properly execute the co de that you've written per the VHDL language standard. Whether that code p erforms the function that you would like it for your "algorithm on a univer sal subject" is up to you to decide. Best of luck on your new endeavors.
Kevin Jennings
Reply to
KJ
e:
that my algorithm on a universal subject is working IN THEORY: with 2 writ e ports for an array, everything is working. By doing so it will save me a lot of energy, cost and time.
e you a lot of energy, cost and time? Ummm...why, are you being lazy? I c an pretty much guarantee that any VHDL simulator will properly execute the code that you've written per the VHDL language standard. Whether that code performs the function that you would like it for your "algorithm on a univ ersal subject" is up to you to decide. Best of luck on your new endeavors.
Hi KJ,
I never said that: "So, you want someone else to run a VHDL simulator for y ou in order to save you a lot of energy, cost and time?"
I will do the simulation by myself to determine if the algorithm is correct .
And I will let others to test if the code implementation on either a Xilinx chip or an Altera chip is working.
A 2 write port memory is a mature technique and I don't have to spend a lot of time to do it myself.
Thank you.
Weng
Reply to
Weng Tianxiang
I paraphrased slightly, but yes you did say that. Read your original post which I quoted you on.
Cool.
Beyond a superficial, quick code review, why would anyone want to do that?
And yet here you are, writing up your own code for two write port memory which you say "is a mature technique". That's pretty much the definition of re-inventing the wheel.
Kevin Jennings
Reply to
KJ
KJ,
I prefer for VHDL grammar to introduce a new statement, specifying an if statement is a second write to an array. Here is a code example on how to introduce such statement:
Here is a code segment showing method, doing 2 writes to an array with 2 different addresses on the same cycle:
p1: process(CLK) is begin if CLK'event and CLK = '1' then if C1 then An_Array(a)
Reply to
Weng Tianxiang
Hi Weng,
Give it up, your are flogging a dead horse, no new language constructs are requires as we already have the correct simulation and synthesis models for decades.
If you have lots of dual port memories to connect use a Generate statement.
Regards, Hans
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Reply to
HT-Lab
ote:
statement is a second write to an array. 'I prefer' is not justification. One needs to provide objective, measurabl e improvement. 'I prefer' doesn't do it.
Yet your example by one measure shows how your new method is worse. Rather than simply typing 'if', now one types 'if_2'. How is that better? The s ame simulation and synthesis results would occur but now any designer is ty ping more to achieve the same...sort of unproductive don't you think? The language gets more complex and produces no objective benefit to anyone...no t the sort of change that benefits.
not having repeatedly to write a 2-write-port memory for different FPGA chi p.
Everybody? How about anybody besides you? Who are these people that "repea tedly to write a 2-write-port memory" rather than writing it once? Those p eople need to learn how design should be done.
This statement simply demonstrates your total lack of ability in design. I f you're writing the same thing 10 times you're doing it the wrong way.
Kevin Jennings
Reply to
KJ
Hans,
Here is an excellent paper dealing with the situation: efficient multi-port memory with FPGA,
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I appreciate the paper very much. I know there is a solution to 2-write memory, but simple "if_2" is a simple solution to inferring to the method.
Weng
Reply to
Weng Tianxiang
array in its full range, including all "else", "elsif" parts. And "if_2" k eyword can only be used in a clocked process.
it, not having repeatedly to write a 2-write-port memory for different FPGA chip.
ent.
rt memory with FPGA,
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pga10.pdf.
emory, but simple "if_2" is a simple solution to inferring to the method.
You have provided a keyword, "if_2" and a code example which is not logical ly correct. I don't see how your keyword solves anything. First, you need to define exactly what the keyword does, which I assume is the same as "if ". Then you need to use examples which are logically correct. Then perhap s you can explain why your new keyword accomplishes something that the exis ting keyword doesn't do already.
It sure seems like you are trying to solve a problem that doesn't exist. C ertainly your initial premise that dual write port RAMs must be instantiate d is not correct. Dual write port RAMs can be inferred as shown in the inf o I linked to in the other thread.
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  Rick C. 

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Reply to
Rick C
Hi Weng,
Yes I know that paper quite well and have used the XOR variant in one of my x86 processors (4W8R). I had no problems implementing it, the standard method is simple and straightforward.
As others have told you multi port memories are well established and understood in our community, there is no need for a special keyword.
Regards, Hans
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Reply to
HT-Lab
rt memory with FPGA,
formatting link
pga10.pdf.
emory, but simple "if_2" is a simple solution to inferring to the method.
If_2 is not the solution to inferring the method by LaForest and Steffan. In a nutshell, what they describe is the bolded text in section 5 (LVT-Base d Multiported memories) where it clearly says "Our approach comprises banks of replicated block RAMs where a mechanism of indirection...". They are not claiming to implement something that implements the two write port hardware description that you presented. There would still need to be code written to implement the LVT approach in order to describe that LVT design . Once that code is written, one would have a multi-port design that one c ould reuse but it would use more logic/memory resources than just a memory.
If you think the LVT based approach is worth using for your design, then wr ite the code to implement an LVT based memory design. Trying to propose 'i f_2' as being some way to implement LVT (or some other alternative approach ) is quite naive on your part.
Kevin Jennings
Reply to
KJ

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