# Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking?

• posted
Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking?
I need help to understand a puzzle:
Merly-type state machine generates outputs which depend on inputs to the state machine and the current states of the state machine, while Moore-type state machine generates outputs which depend only on the current states of the state machine.
Am I right if I treat a Merly-type state machine as a Moore-type state machine plus an independent combinational logic which has the same inputs to the state machine and the Moore-type state machine's state outputs?
If I am right, why the paper "Automatic synthesis of lower power gated-clock finite state machine"

says (p.632, 2nd column, last section) "The knowledge of the state and the input is not sufficient to individuate the conditions when the clock can be stopped."
Thank you.
Weng
• posted
nes are important on how to stop clocking?
state machine and the current states of the state machine, while Moore-type state machine generates outputs which depend only on the current states of the state machine.
achine plus an independent combinational logic which has the same inputs to the state machine and the Moore-type state machine's state outputs?
ock finite state machine"
un96pg630.pdf
e input is not sufficient to individuate the conditions when the clock can be stopped."
I believe any Moore type FSM can be converted to any Mealy type FSM and vic e versa. That would imply that the two types of FSM should be equivalent i n this consideration.
However, your question actually has nothing to do with the distinction of t he two types of FSM.
I would also point out the definition of the Mealy type FSM is often not we ll specified. While they define it as having outputs dependent on the inpu ts as well as the state, I find they are usually implemented with registere d outputs. This effectively makes them Moore type FSM even if those output s are not provided as inputs to the FSM logic.
The paper PDF file does not allow copying of text, so I won't go into this much, but this paper has fundamental errors I believe. For one, they menti on there are "conditions such that the outputs and next state do not change ". Then they go on to say stopping the clock will save power in the combin ational logic because the outputs of registers are prevented from changing. What registers would those be??? If the outputs and registers are not ch anging, what would be changing that would make the combinational logic cons ume power???
Finally, I would submit it is very easy to determine if a FF should be cloc ked or not. Simply compare the D input to the Q output. If they are the s ame, gate the clock. If they are different enable the clock. BTW, this ef fectively turns the D FF into a toggle FF.
Isn't this whole thing a bit of a DUH! Not very patentable since it is obv ious to anyone skilled in the field.
BTW, how is the wave pipelining thing going?
```--
Rick C.

- Get 1,000 miles of free Supercharging ```
• posted
hines are important on how to stop clocking?
e state machine and the current states of the state machine, while Moore-ty pe state machine generates outputs which depend only on the current states of the state machine.
machine plus an independent combinational logic which has the same inputs to the state machine and the Moore-type state machine's state outputs?
clock finite state machine"
6Jun96pg630.pdf
the input is not sufficient to individuate the conditions when the clock ca n be stopped."
ice versa. That would imply that the two types of FSM should be equivalent in this consideration.
the two types of FSM.
well specified. While they define it as having outputs dependent on the in puts as well as the state, I find they are usually implemented with registe red outputs. This effectively makes them Moore type FSM even if those outp uts are not provided as inputs to the FSM logic.
s much, but this paper has fundamental errors I believe. For one, they men tion there are "conditions such that the outputs and next state do not chan ge". Then they go on to say stopping the clock will save power in the comb inational logic because the outputs of registers are prevented from changin g. What registers would those be??? If the outputs and registers are not changing, what would be changing that would make the combinational logic co nsume power???
ocked or not. Simply compare the D input to the Q output. If they are the same, gate the clock. If they are different enable the clock. BTW, this effectively turns the D FF into a toggle FF.
bvious to anyone skilled in the field.
Hi Rick,
Thank you very much! I fully agree with your opinion, especially your follo wing opinion:
e clock. If they are different enable the clock. BTW, this effectively tu rns the D FF into a toggle FF.
Weng
• posted
nes are important on how to stop clocking? Refer to my post on comp.lang.vhdl at