How do big compagnies use Verilog/VHDL for processor designs?

I have a question on how big companies like Intel/AMD use VHDL and Verilog internally for their processors.
For example, if they implement an ALU. Do they implement the ALU on an RTL-level or do they instantiate hand-optimized components (adder, barrel shifter, multiplier).
Basically, does the synthesizer actually do something or does it only connect hand-optimized components?
Regards
Reply to
Benjamin Couillard
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You might get useful answers here in comp.arch - there are regulars there who work (or worked) for companies like AMD in processor design.
My understanding - which could be /very/ flawed, so don't trust it - is that for something as big and complex as a big CPU, people rarely use "raw" Verilog or VHDL. They use higher level languages that generate lower level languages or RTL output. For an example in the open source world (where information is easier to obtain!), look at
Reply to
David Brown
There's a spectrum of implementations, but one methodology is:
- code in HDL, simulate, etc. - hand layout the crucial parts - register banks, ALUs, etc. - extract the circuit and timing from the hand layout and check for equivalence.
Hand layout is expensive even with good tooling, circuit extraction ditto, so getting as much as possible to go automatically from HDL to silicon matters to most companies.
Reply to
Tim

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