Re: Program Counter in Verilog. Case not working.

All possible case values need to be in the code. pc_mode[2:0] allows for 8 values and your code only has 5. You can add a one default case for the ones you don't need instead of adding each individually. For instance:

default: begin // do something here end

Generally in an edge clocked 'always@' block you should use non blocking assignments. In other words use <= instead of just the = sign.

For instance:

pc_value[7:0] <= 8'b0000_0000;

temp[7:0] = 8'bzzzz_zzzz;

There may also be a problem with this.

temp[7:0] is an internal register in your module. It is my experience that an internal register can't be tristated.

One other thing:

I believe you should have each case statement actually do something.

I'm a hobbyist programmer not an expert but maybe this will help.

Charlie

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Charlie
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Thank you for the clarification. You are, of course, correct. I should have stated that my answer referred to the tools he was using (8bitworkshop). With that tool the errors he encountered were resolved by adding all possible case values or a default case.

For what it is worth, his code synthesizes without errors using Xilinx ISE.

Okay, I didn't know that. I just always put a default case in there unless all case values are used.

It may be useful to have a default that displays an error message.

Agreed.

I agree but comp.lang.verilog would be a better choice, I think. ;-)

Charlie

Reply to
Charlie

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