Re: Program Counter in Verilog. Case not working.

Hello All,

>
> I'm just getting started with Verilog.
> I created the following Programs Counter for a simple Stack Machine.
> The PC is an 8-bit register that stores the address of the command being executed.
> The clock pulse at the positive edge of the clock signal (except mode = 2).
> If mode = 0 reset PC to 0
> If mode = 1, set the PC value to be equal to the value in the data bus.
> If mode = 2, write the PC value to the data bus.
> If mode = 3 do nothing (value z at data bus)
> If mode = 4, increase PC by one unit.
>
> Here is a GIST with the code...
>

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I'm testing it at:

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> And I getting errors on:
> case( pc_mode[2:0] )
> Case values incompletely covered (example pattern 0x5)

All possible case values need to be in the code. pc_mode[2:0] allows for 8 values and your code only has 5. You can add a one default case for the ones you don't need instead of adding each individually. For instance:

default: begin // do something here end

3'b000:
> begin
> pc_value[7:0] = 8'b0000_0000;
> (clock_divider.v:21) 20: Blocking assignments (=) in sequential (flop or latch) block

Generally in an edge clocked 'always@' block you should use non blocking assignments. In other words use <= instead of just the = sign.

For instance:

pc_value[7:0] <= 8'b0000_0000;

temp[7:0] = 8'bzzzz_zzzz;

There may also be a problem with this.

temp[7:0] is an internal register in your module. It is my experience that an internal register can't be tristated.

> Any ideas?

One other thing:

I believe you should have each case statement actually do something.

I was trying to run it as an if statement but ran into this...
>

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And I decided to go with the case statement, but it does not seem to work or it's not properly validated in the tool...
>
> Cheers
>
> Jose.
>

I'm a hobbyist programmer not an expert but maybe this will help.

Charlie