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xilinx webpack simulation problem (latch in place of logic)

Hi group, When I am developing code for a hobby project, I find that ModelSim XE II/Starter 5.7c (came with Xilinx Webpack 6.1.03i infered unnecessary latch in place of logic. It is a before-synthesis simulation, not a post-fit simulation. Here is the sample code (complete and compiles) and the simulated result is posted at . In the program I combined signals (EAL0 and EAL2) to make the code clean. It might be that I made some mistake that I did't know of. I examined the program over and over and still could not find where the problem is. Any idea? Thanks.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TEST is Port ( RESULT: out std_logic_vector(1 downto 0); TEMP: INOUT std_logic_vector(1 downto 0); EAL0: in std_logic; EAL2: in std_logic ); end TEST; architecture Behavioral of TEST is begin TEMP

Reply to
vax, 9000
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One grid on the simulated waveform represents 10ns.

--vax, 9000

Reply to
vax, 9000

Fix your sensitivity list. It should be: TEST_PROCESS:process (temp)

Regards, Jim

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Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
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Reply to
Jim Lewis

That's where the problem was. After changing the sensitivity list, the problem is gone. Thank you very much.

--vax, 9000

Reply to
vax, 9000

In general, the process sensitivity list normally has signals from the right side of an assignment statement, or signals that would alter the flow of statements. I think you need to remove EAL0 and EAL2 from the sensitivity list and put in signal temp. For an event based simulator (Modelsim), when EAL0 or EAL2 change, because this is a functional simulation, (e.g. no component or routing delays, the value of temp is scheduled to change some small delta time in the future. When the simulator hits the process statement, the change in EAL0 or EAL2 triggers the process, but temp has not changed yet because it is not scheduled to change until a little bit in the future. When temp does change, since it is not in the sensitivity list, the process does not get triggered.

Synthesizers that I have used modify the sensitivity list accordingly, and issue a warning to the user. This would cause the functional simulation to mismatch against the gate level one.

I use emacs because it has a great VHDL package that automatically updates the sensitivity list for you.

Hope this helps,

Newman

Reply to
newman

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