XILINX Webpack VHDL synthesis question (unnecessary MUX infered)

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vax, 9000 21 years ago

Hi group, When I am developing code for a hobby project, I find that XILINX webpack infers unnecessary MUX. I suspect that the MUX eats resource so I'd like to remove it to pack more function into the XC95144XL target. I am using the version 6.1. Here is the sample code (complete and compiles) and the synthesized schematic is posted at . I think ADDR_NEXT can be connected to D only and HOST_DATA can be connected to pre-set/clr only. Any idea? Thanks.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity busmaster is Port ( ADDR: out std_logic_vector(7 downto 0); ADDR_CLK_I: in std_logic; ADDR_NEXT: in std_logic_vector(7 downto 0); HOST_DATA: in std_logic_vector(7 downto 0); HOST_CSWR: in std_logic ); end busmaster; architecture Behavioral of busmaster is begin ADDR_UPDATE: process (HOST_DATA,HOST_CSWR,ADDR_CLK_I) begin -- process if HOST_CSWR = '0' then ADDR

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rickman 21 years ago

I agree 100%. The mux is pointless. In essence the mux combines the two sets of signals and the set/clear logic is demuxing them again. You DO need the and gates on the set/clear inputs since according to your code, HOST_DATA is a signal and not a constant and is only used when HOST_CSWR is '0'.

However, in a CPLD, I am not sure that the mux uses additional resources. The set/clear and gates will use some of the terms in the array, so I don't think any of the other terms will be available for other functions. Anyone know for sure?

Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX

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Jim Lewis 21 years ago

vax, 9000, Cool Results. For some reason the synthesis tool got lost.

Some devices do not have an asynchronus set. Hence, they implement it with an asynchronous load and '1' on the data lines when asynchronous set is specified. However, if this was truely the case, then why not simplify the PRE input and not use the CLR input. Perhaps there is a bug in the synthesis part library.

Are you sure you really want an asynchronous load. Typically I only do asynchronous set and clears. All normal functionality is synchronous to clock.

Cheers, Jim

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

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Alan Fitch 21 years ago

XILINX webpack

I'd like to

synthesized

ADDR_NEXT can

pre-set/clr only.

As an experiment, what happens if you take HOST_DATA out of the sensitivity list? For a standard clocked process template I'd only expect to see asynchronous control signals and the clock in the sensitivity list, e.g.

addr_update:process(host_cswr, addr_clk_i) begin ...

regards Alan

Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.

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Klaus Falser 21 years ago

This is an error I tried to tell Xilinx a long time ago. My FAE told me it will be fixed in version 7.1.

In the mean time you have to infer a FDCP primitive and attach your signals directly to the inputs.

Best regards Klaus Falser

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vax, 9000 21 years ago

The result does not change (mux infered). Furthermore, I get a warming,

WARNING:Xst:819 - C:/busmaster/busmaster.vhd line 16: The following signals are missing in the process sensitivity list: HOST_DATA.

Thanks. VAX, 9000

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rickman 21 years ago

That would not be correct in this case because the signal ADDR will change on a change of HOST_DATA while HOST_CSWR is low. So HOST_DATA does need to be in the sensitivity list. Normally the async control is just a clear or set so the data value is fixed, not a signal.

Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX

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Jim Lewis 21 years ago

vax, 9000,

My first recommendation is to re-write it so the load is synchronous to clock: ADDR_UPDATE: process (HOST_DATA,HOST_CSWR,ADDR_CLK_I) begin -- process if ADDR_CLK_I'event and ADDR_CLK_I = '1' then if HOST_CSWR = '0' then ADDR

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Alan Fitch 21 years ago

HOST_DATA

is

Oh yes, sorry, brain failure :-)

Alan

Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.

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XILINX Webpack VHDL synthesis question (unnecessary MUX infered)

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