problem with shift operation

Apr 21, 2006 1 Replies

I hav the follwoing simple code which does left shifting operation.



library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity counter is port ( q: inout STD_LOGIC_VECTOR (3 downto 0); clock: in STD_LOGIC; reset: in STD_LOGIC; en: in STD_LOGIC ); end counter;


architecture counter of counter is signal count:std_logic_vector(3 downto 0):="0000"; begin



process(clock,reset) begin



if reset='0' then count


Hi, Instead of declaring count as signal , you declare it as variable and check out. I think it should work. Normally the signal gets updated at the end of the process. The use of variable is best suited for your case. Regards, Srikanth

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