VHDL-Xilinx-Simulation (signal not connected to port) ?

Hi.

How to simulate (observe) signals not connected to port (Xiilinx ISE WebPack-ModelSim XE). For example signal counter in project test.vhd.

Best regards Jarek

-----test.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Test is Port ( clock: in std_logic; -- system clock (25 MHz) resetn: in std_logic; -- active low reset c_out: out std_logic); end Test;

architecture Behavioral of Test is

signal counter: std_logic_vector(3 downto 0); begin

COUNT: process (clock, resetn) begin if (resetn = '0') then counter '0'); elsif (clock'event and clock = '1') then counter resetn, c_out => c_out );

clock