Multiplier in Xilinx

What's 65535 * 15 ?

I asked you the leading question and you gave me background, not an answer.

The 20-bit value efff1 cannot be represented in 16 bits.

The question you need to ask yourself is what accuracy you need in your parameter value that you're trying to restrict to 16 bits. Perhaps you can get by with 9 bits. It's ENTIRELY dependent on your needs and NOT something we can give you advice on without knowing the details of your needs. The details you gave only give a glimpse at issues that are probably too detailed to communicate effectively online.

Are you familiar with the concepts of Error Analysis and Quantization Error?

- John_H

You are dealing with binary fractions, not integers, right? That is, numbers between 0 and 1 (or -1 to 1)? In your case, just take the leftmost 16 bits of the 20 bit result.

-Jeff

No, i am dealing with integers and binary fractions. I cannot only take the leftmost 16bits. It will result in the wrong.

Then either : - Your application ensure by design that the result is always smaller than 65535 and you can just take the rightmost 16 bits. - You must have a result on 20 bits (deal with it !) - You're screwed

Sylvain

I am coming into this discussion late, but if you ha 20 bit result (prod[19:0]) from a 4 and 16 bit signed fractional mult, you would want to keep prod[18:3] to keep it in the range of -1 to 1. You end up with two sign bits when you multiply two signed fractions together so you can throw one of them away.

Note, you should also have a rounding scheme for prod[2:0] to keep it as accurate as possible.

Tom

The multipliers in Altera Stratix FPGAs can be operated in a Q1.1 fractional binary mode that I have found to be useful in a previou project.

If the Xilinx multipliers can be operated in a similar mode it might b a/the answer to your problem.

Thanks for all your answers. 'lamda' is within (-1,1) and transmitted into fpga board from matalab. Before it transmitted to uart, lamda has been changed to Q15 format. I need 'lamda' update correspording to the interative times from 1 to 5. I guess I am wrong here. I cannot direct use the integer * Q15 binary. Coz the 'lamda' is binary and has been enlarged 2*16 whereas interative number is not.

I did not know how to figure it out so far. So can I just generate the 5 interative numbers and multiply from matlab and transformed to Q15 format, then transmit to the fpga. (It looks so silly)

Also the Q15 updated lamda will mulitply another Q15 parameter. 2 signed prod[15 0] multiply. If I want to keep 32 bits. Is it correct that I just keep prod[30 0] & '0' as my result. I removed the first sign.

One more thing, the type in the multiplier is 'signed', why i still can use 'std_logic_vector'. Is it same? And I don't need to convert 'std_logic_vector' to 'signed'.

The answer is quite simple.

For the equation: q=a*b

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_BIT.ALL;

signal t : std_logic_vector(19 downto 0); signal q : std_logic_vector(15 downto 0); signal a : std_logic_vector(3 downto 0); siganl b : std_logic_vector(15 downto 0);