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Need Help

Hello al

I am working on the design of a simple RAM module for m

microcontroller design. In the VHDL simulation data is not gettin loaded into the bidirectional IO bus what might be the problem wit my simple design. The program is given below:

library ieee

use ieee.std_logic_1164.all use ieee.std_logic_arith.all use ieee.std_logic_unsigned.all

entity sram i

port( clock: in std_logic; enable: in std_logic rwbar: in std_logic; -- (1 - Read, 0 - Write addr: in std_logic_vector(4 downto 0); data: inout std_logic_vector(15 downto 0 ) end sram

architecture sram_arch of sram i

type ram_type is array (0 to 31) of std_logic_vector(15 downto 0) signal tmp_ram: ram_type begi process(clock begi if(clock='1' and clock'event) the

if(enable='1') the

if(rwbar='1') the data '0')); -- rst_b ever bi els if (clk'event and clk = '1' ) the data_bus < to_stdlogicvector(gpram(conv_integer(unsigned(addr_bus)))) if ram_wr_i='1' the gpram(conv_integer(unsigned(addr_bus))) : to_bitvector(data_bus) end if end if end if end process p_readwrite; end sim

I am not able to sort out my mistake. Please help me out with m

code

Vasan

Reply to
Vasant
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You should instantiate the RAM module directly into your code, either as a component or as a macro. See this link (.ppt)

formatting link

Milind

Reply to
milind.parelkar

for inferring bram see the code below-

----code------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity sram is port( clock: in std_logic; enable: in std_logic; rwbar: in std_logic; -- (1 - Read, 0 - Write) addr: in std_logic_vector(4 downto 0); data: inout std_logic_vector(15 downto 0) ); end sram;

architecture sram_arch of sram is type ram_type is array (0 to 31) of std_logic_vector(15 downto 0); signal tmp_ram: ram_type; begin process(clock) begin if(clock='1' and clock'event) then --if(enable='1') then if(rwbar='1') then data

Reply to
Neo

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