Hi, I am wondering if I wrote the timing constraint properly. I have 2 clocks (clk, phy_rx_clk) coming in from the outside. clk is used to run part of my FF phy_rx_clk goes in a dcm and I use CLK0 and CLK180 output of the dcm. The data coming into the FPGA will have a minimum setup time 1.4 ns and minimum hold time 1.2 ns. CLK0 and CLK180 are used on DDR clock inputs. I need to make sure the setup and hold time will not be violated so i setup the constraint file as follows. I was wondering if somebody could check it out and let me know if I am doing anything wrong.
NET "clk" TNM_NET = "clk_grp"; TIMESPEC "TS_clk" = PERIOD "clk_grp" 8 ns HIGH 50 %;
NET "phy_rx_clk" TNM_NET = "phy_rx_clk_grp"; TIMESPEC "TS_phy_rx_clk" = PERIOD "phy_rx_clk_grp" 8 ns HIGH 50 %;
NET "CLK0_rx" TNM = "CLK0_rx_grp"; NET "CLK180_rx" TNM = "CLK180_rx_grp";
TIMEGRP "CLK0_rx_grp_ddr" = RISING "CLK0_rx_grp"; # Check wrt rising edge TIMEGRP "CLK180_rx_grp_ddr" = RISING "CLK180_rx_grp"; # Check wrt rising edge
OFFSET = IN 1.4 ns BEFORE "phy_rx_clk" TIMEGRP "CLK0_rx_grp_ddr"; #1.4ns setup
OFFSET = IN 1.2 ns AFTER "phy_rx_clk" TIMEGRP "CLK0_rx_grp_ddr"; #1.2ns hold
For some reason I get WARNING:ConstraintSystem:65 - Constraint [.\ethernet.pcf(556)] overrides constraint [.\ethernet.pcf(554)].
I cannot figure out why. Anybody can enlighten me. I am using Xilinx ISE 8.2