Hi, I have a design for a custom made board with Spartan 3 xc3s1000 on it. There is a SATA controller on the same board. Since this SATA controller uses PCI interface to communicate to the outer world, I have used opencores PCI bridge inside FPGA to communicate with SATA controller. The synthesized design works fine however I do get some initialization errors at startup. It seems more like a timing problem to me. When analyzed critically, I observed that many of the timing constraints are being ignored by the synthesis tool (ISE 7.1i and ISE
9.2i). I have multiple clocks in my design and there are clock crossing domains. I have marked those domaing and TIGed them in the UCF. I am suspecting that the problem that I am facing is becuase of these ignored timing constraints. The portion of the UCF file where these timings contraints are written is pasted below. ======================================= INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD"; INST "AD" TNM = "PCI_AD";TIMEGRP "PCI_AD" OFFSET = IN 7 ns BEFORE "CLK_66"; TIMEGRP "PCI_AD" OFFSET = OUT 11 ns AFTER "CLK_66";
INST "CBE" TNM = "PCI_CBE"; INST "CBE" TNM = "PCI_CBE"; INST "CBE" TNM = "PCI_CBE"; INST "CBE" TNM = "PCI_CBE";
TIMEGRP "PCI_CBE" OFFSET = IN 7 ns BEFORE "CLK_66"; TIMEGRP "PCI_CBE" OFFSET = OUT 11 ns AFTER "CLK_66";
NET "DEVSEL" OFFSET = IN 7 ns BEFORE "CLK_66"; NET "DEVSEL" OFFSET = OUT 11 ns AFTER "CLK_66";
NET "FRAME" OFFSET = IN 7 ns BEFORE "CLK_66"; NET "FRAME" OFFSET = OUT 11 ns AFTER "CLK_66";
NET "SATA_GNT" OFFSET = IN 10 ns BEFORE "CLK_66";
NET "IRDY" OFFSET = IN 7 ns BEFORE "CLK_66"; NET "IRDY" OFFSET = OUT 11 ns AFTER "CLK_66";
NET "PAR" OFFSET = IN 7 ns BEFORE "CLK_66"; NET "PAR" OFFSET = OUT 11 ns AFTER "CLK_66";
NET "PERR" OFFSET = IN 7 ns BEFORE "CLK_66"; NET "PERR" OFFSET = OUT 11 ns AFTER "CLK_66";
NET "SATA_REQ" OFFSET = OUT 12 ns AFTER "CLK_66";
NET "SERR" OFFSET = OUT 11 ns AFTER "CLK_66";
NET "STOP" OFFSET = IN 7 ns BEFORE "CLK_66"; NET "STOP" OFFSET = OUT 11 ns AFTER "CLK_66";
NET "TRDY" OFFSET = IN 7 ns BEFORE "CLK_66"; NET "TRDY" OFFSET = OUT 11 ns AFTER "CLK_66";
NET "SATA_IDSEL" OFFSET = IN 7 ns BEFORE "CLK_66";
######################################################################################################
NET "CLK_125" TNM_NET = "CLK_125"; TIMESPEC "TS_CLK_125" = PERIOD "CLK_125" 8 ns HIGH 50 %; NET "CLK_66" TNM_NET = "CLK_66"; TIMESPEC "TS_CLK_66" = PERIOD "CLK_66" 14 ns HIGH 50 %; NET "uc_clk" TNM_NET = "uc_clk"; TIMESPEC "TS_uc_clk" = PERIOD "uc_clk" 1000 ns HIGH 50 %;
NET "tx_clk" TNM_NET = "tx_clk"; TIMESPEC "TS_tx_clk" = PERIOD "tx_clk" 40 ns HIGH 50 %;
NET "rx_clk" TNM_NET = "rx_clk"; TIMESPEC "TS_rx_clk" = PERIOD "rx_clk" 40 ns HIGH 50 %;
#################### # Domains Created #################### # domain_clk_33 # domain_clk_uc # domain_clk_adc # domain_clk_66 # domain_emac_clk_rx # domain_emac_clk_tx
NET "uc_clk" TNM_NET = "domain_clk_uc"; NET "CLK_66" TNM_NET = "domain_clk_66"; NET "CLK_33" TNM_NET = "domain_clk_33"; #NET "CLK_125" TNM_NET= "domain_clk_125" NET "CLK_ADC" TNM_NET = "domain_clk_adc"; NET "tx_clk" TNM_NET = "domain_clk_tx"; NET "rx_clk" TNM_NET = "domain_clk_rx";
TIMESPEC "TS_clk_uC_to_clk_66" = FROM "domain_clk_uc" TO "domain_clk_66" TIG; TIMESPEC "TS_clk_uC_to_clk_33" = FROM "domain_clk_uc" TO "domain_clk_33" TIG; #TIMESPEC "TS_clk_uC_to_clk_125" = FROM "domain_clk_uc" TO "domain_clk_125" TIG TIMESPEC "TS_clk_uC_to_clk_adc" = FROM "domain_clk_uc" TO "domain_clk_adc" TIG; TIMESPEC "TS_clk_uC_to_clk_tx" = FROM "domain_clk_uc" TO "domain_clk_tx" TIG; TIMESPEC "TS_clk_uC_to_clk_rx" = FROM "domain_clk_uc" TO "domain_clk_rx" TIG;
TIMESPEC "TS_clk_66_to_clk_uc" = FROM "domain_clk_66" TO "domain_clk_uc" TIG; TIMESPEC "TS_clk_66_to_clk_33" = FROM "domain_clk_66" TO "domain_clk_33" TIG; #TIMESPEC "TS_clk_66_to_clk_125" = FROM "domain_clk_66" TO "domain_clk_125" TIG TIMESPEC "TS_clk_66_to_clk_adc" = FROM "domain_clk_66" TO "domain_clk_adc" TIG; TIMESPEC "TS_clk_66_to_clk_tx" = FROM "domain_clk_66" TO "domain_clk_tx" TIG; TIMESPEC "TS_clk_66_to_clk_rx" = FROM "domain_clk_66" TO "domain_clk_rx" TIG;
TIMESPEC "TS_clk_33_to_clk_uc" = FROM "domain_clk_33" TO "domain_clk_uc" TIG; TIMESPEC "TS_clk_33_to_clk_66" = FROM "domain_clk_33" TO "domain_clk_66" TIG; #TIMESPEC "TS_clk_33_to_clk_125" = FROM "domain_clk_33" TO "domain_clk_125" TIG TIMESPEC "TS_clk_33_to_clk_adc" = FROM "domain_clk_33" TO "domain_clk_adc" TIG; TIMESPEC "TS_clk_33_to_clk_tx" = FROM "domain_clk_33" TO "domain_clk_tx" TIG; TIMESPEC "TS_clk_33_to_clk_rx" = FROM "domain_clk_33" TO "domain_clk_rx" TIG;
TIMESPEC "TS_clk_adc_to_clk_uc" = FROM "domain_clk_adc" TO "domain_clk_uc" TIG; TIMESPEC "TS_clk_adc_to_clk_33" = FROM "domain_clk_adc" TO "domain_clk_33" TIG; #TIMESPEC "TS_clk_adc_to_clk_125"= FROM "domain_clk_adc" TO "domain_clk_125" TIG TIMESPEC "TS_clk_adc_to_clk_66" = FROM "domain_clk_adc" TO "domain_clk_66" TIG; TIMESPEC "TS_clk_adc_to_clk_tx" = FROM "domain_clk_adc" TO "domain_clk_tx" TIG; TIMESPEC "TS_clk_adc_to_clk_rx" = FROM "domain_clk_adc" TO "domain_clk_rx" TIG;
TIMESPEC "TS_clk_tx_to_clk_uc" = FROM "domain_clk_tx" TO "domain_clk_uc" TIG; TIMESPEC "TS_clk_tx_to_clk_33" = FROM "domain_clk_tx" TO "domain_clk_33" TIG; #TIMESPEC "TS_clk_tx_to_clk_125" = FROM "domain_clk_tx" TO "domain_clk_125" TIG TIMESPEC "TS_clk_tx_to_clk_adc" = FROM "domain_clk_tx" TO "domain_clk_adc" TIG; TIMESPEC "TS_clk_tx_to_clk_66" = FROM "domain_clk_tx" TO "domain_clk_66" TIG; TIMESPEC "TS_clk_tx_to_clk_rx" = FROM "domain_clk_tx" TO "domain_clk_rx" TIG;
TIMESPEC "TS_clk_rx_to_clk_uc" = FROM "domain_clk_rx" TO "domain_clk_uc" TIG; TIMESPEC "TS_clk_rx_to_clk_33" = FROM "domain_clk_rx" TO "domain_clk_33" TIG; #TIMESPEC "TS_clk_rx_to_clk_125" = FROM "domain_clk_rx" TO "domain_clk_125" TIG TIMESPEC "TS_clk_rx_to_clk_adc" = FROM "domain_clk_rx" TO "domain_clk_adc" TIG; TIMESPEC "TS_clk_rx_to_clk_tx" = FROM "domain_clk_rx" TO "domain_clk_tx" TIG; TIMESPEC "TS_clk_rx_to_clk_66" = FROM "domain_clk_rx" TO "domain_clk_66" TIG;
NET "CLK_33_OBUF" TNM_NET = "CLK_33_OBUF"; TIMESPEC "TS_CLK_33_OBUF" = PERIOD "CLK_33_OBUF" 30.03 ns HIGH 50 %;
TIMESPEC "TS_F2F" = FROM "FFS" TO "FFS" 14 ns;
//
*********************************************************************=======================// This is what I get from ISE 9.2 i during implementation process.///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
WARNING:Timing:3223 - Timing constraint PATH "TS_U_TO_D_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_uC_to_clk_33_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_uC_to_clk_adc_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_uC_to_clk_tx_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_uC_to_clk_rx_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_66_to_clk_adc_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_33_to_clk_uc_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_33_to_clk_66_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_33_to_clk_adc_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_33_to_clk_tx_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_33_to_clk_rx_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_adc_to_clk_uc_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_adc_to_clk_33_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_adc_to_clk_66_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_adc_to_clk_tx_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_adc_to_clk_rx_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_tx_to_clk_uc_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_tx_to_clk_33_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_tx_to_clk_adc_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_tx_to_clk_rx_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_rx_to_clk_uc_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_rx_to_clk_33_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_rx_to_clk_adc_path" TIG; ignored during timing analysis. WARNING:Timing:3223 - Timing constraint PATH "TS_clk_rx_to_clk_tx_path" TIG; ignored during timing analysis. WARNING:Timing:3175 - CLK_66 does not clock data from STOP WARNING:Timing:3225 - Timing constraint COMP "STOP" OFFSET = IN 7 ns BEFORE COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3175 - CLK_66 does not clock data to STOP WARNING:Timing:3225 - Timing constraint COMP "STOP" OFFSET = OUT 11 ns AFTER COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3175 - CLK_66 does not clock data from DEVSEL WARNING:Timing:3225 - Timing constraint COMP "DEVSEL" OFFSET = IN 7 ns BEFORE COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3175 - CLK_66 does not clock data to DEVSEL WARNING:Timing:3225 - Timing constraint COMP "DEVSEL" OFFSET = OUT 11 ns AFTER COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3175 - CLK_66 does not clock data to IRDY WARNING:Timing:3225 - Timing constraint COMP "IRDY" OFFSET = OUT 11 ns AFTER COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3175 - CLK_66 does not clock data to TRDY WARNING:Timing:3225 - Timing constraint COMP "TRDY" OFFSET = OUT 11 ns AFTER COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3175 - CLK_66 does not clock data from PERR WARNING:Timing:3225 - Timing constraint COMP "PERR" OFFSET = IN 7 ns BEFORE COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3175 - CLK_66 does not clock data to PERR WARNING:Timing:3225 - Timing constraint COMP "PERR" OFFSET = OUT 11 ns AFTER COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3175 - CLK_66 does not clock data from PAR WARNING:Timing:3225 - Timing constraint COMP "PAR" OFFSET = IN 7 ns BEFORE COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3175 - CLK_66 does not clock data to PAR WARNING:Timing:3225 - Timing constraint COMP "PAR" OFFSET = OUT 11 ns AFTER COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3175 - CLK_66 does not clock data to FRAME WARNING:Timing:3225 - Timing constraint COMP "FRAME" OFFSET = OUT 11 ns AFTER COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3175 - CLK_66 does not clock data to SERR WARNING:Timing:3225 - Timing constraint COMP "SERR" OFFSET = OUT 11 ns AFTER COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3175 - CLK_66 does not clock data to SATA_REQ WARNING:Timing:3225 - Timing constraint COMP "SATA_REQ" OFFSET = OUT
12 ns AFTER COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3175 - CLK_66 does not clock data from SATA_IDSEL WARNING:Timing:3225 - Timing constraint COMP "SATA_IDSEL" OFFSET = IN 7 ns BEFORE COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3175 - CLK_66 does not clock data from SATA_GNT WARNING:Timing:3225 - Timing constraint COMP "SATA_GNT" OFFSET = IN 10 ns BEFORE COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3224 - The clock CLK_66 associated with TIMEGRP "PCI_AD" OFFSET = IN 7 ns BEFORE COMP "CLK_66"; does not clock any registered input components. WARNING:Timing:3225 - Timing constraint TIMEGRP "PCI_AD" OFFSET = IN 7 ns BEFORE COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3224 - The clock CLK_66 associated with TIMEGRP "PCI_AD" OFFSET = OUT 11 ns AFTER COMP "CLK_66"; does not clock any registered output components. WARNING:Timing:3225 - Timing constraint TIMEGRP "PCI_AD" OFFSET = OUT 11 ns AFTER COMP "CLK_66"; ignored during timing analysis WARNING:Timing:3224 - The clock CLK_66 associated with TIMEGRP "PCI_CBE" OFFSET = OUT 11 ns AFTER COMP "CLK_66"; does not clock any registered output components. WARNING:Timing:3225 - Timing constraint TIMEGRP "PCI_CBE" OFFSET = OUT 11 ns AFTER COMP "CLK_66"; ignored during timing analysis //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////The question is why the tool is ignoring almost all timing constraints? My second question is, OFFSET IN OFFSET OUT contraints are used with respect to clock which is a global clock and locked to some GCLK pin. These constraints cannot be applied with respect to clocks which are genreated inside the FPGA. If I want to run the PCI on 33 MHz, I will get a divided by 2 version of the 66 MHz clock which is an external clock in my case. In that case, how would I apply the OFFSET IN OFFSET out constraints with respect to teh 33 MHz clock? I tried to use FROM TO constraints, is that OK? for example
INST "FRAME" TNM = "PCI_FRAME"; TIMESPEC "TS_PCI_FRAME0" = FROM "PCI_FRAME" TO "PADS" 11 ns; TIMESPEC "TS_PCI_FRAME1" = FROM "PADS" TO "PCI_FRAME" 7 ns;
Thanks in advance for reading such a long posting. I hope people out there have answers to my queries.
Regards Farhan