Memec Virtex-4 LX25 LC

Hello, I am working on the Virtex-4 LX25 LC for a project.

Whenever I create edk project using Base Design builder for this and generate the bitstream I get the following error

Timing constraints have not been met.

NET "fpga_0_Ethernet_MAC_PHY_rx_clk" PERIOD = 40 nS HIGH 14 nS

NET "fpga_0_Ethernet_MAC_PHY_tx_clk" PERIOD = 40 nS HIGH 14 nS

TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "RXCLK_GRP_Ethernet_ MAC" 6 nS

I have reduced the system frequency to 75Mhz and reduced the above the 3rd constraint to 6.5ns to get generate the bitstream using timing packing with high effort level for map and par.

But when I add extra user IP, the timing constraints cannot be met again.

I would appreciate any help in solving this problem.

My setup is ISE and EDK 6.3i with SP2.

Best Regards, Shakith

Reply to
Shakith
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Adding the IP will change the place and route implementation. Depending on what you are doing you may be adding or generating logic paths with lots of level of LUTs etc which are hard to meet timing on.

If you run Timing Analyser it will tell you the paths that fail and you can work out where your problems are and possibly fix them by adding pipelining of the logic or simply changing the logic you may be able to meeting.

Another approach is to use multiple place and route which ISE supports. Takes time but may find a timing solution without you delving into the logic.

Another thing to consider is floorplanning your design which may assist the p&r tools to make a better, faster, solution.

One general comment is that the first 2 constraints appear to be clocks with a poor mark/space ratio. Are your clocks that bad? If you have logic that uses both edges of the clock then you may be making the p&r task much more difficult as it will be trying to make timing on effectively 71MHz rather than the 50 MHz of a "perfect" clock.

John Adair Enterpoint Ltd. - Home of MINI-CAN. Low Cost PCI Development Board.

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Reply to
John Adair

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