Hello, I am working on the Virtex-4 LX25 LC for a project.
Whenever I create edk project using Base Design builder for this and generate the bitstream I get the following error
Timing constraints have not been met.
NET "fpga_0_Ethernet_MAC_PHY_rx_clk" PERIOD = 40 nS HIGH 14 nS
NET "fpga_0_Ethernet_MAC_PHY_tx_clk" PERIOD = 40 nS HIGH 14 nS
TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "RXCLK_GRP_Ethernet_ MAC" 6 nS
I have reduced the system frequency to 75Mhz and reduced the above the 3rd constraint to 6.5ns to get generate the bitstream using timing packing with high effort level for map and par.
But when I add extra user IP, the timing constraints cannot be met again.
I would appreciate any help in solving this problem.
My setup is ISE and EDK 6.3i with SP2.
Best Regards, Shakith