Hello group,
I'm working on a design with two external clocks in a xc2v3000. Clocks are dspclk and sysclk, and signals crossing clock domains come from dspclk and go to sysclk only.
Apart from using blockrams, some signals from dspclk cross to sysclk using mults and dffs-based synchronizers. I've used the following UCF constraints to cover those signals crossing clocks:
TIMEGRP "TRG_busnoffs" = TNM_dspclk EXCEPT FFS; TIMEGRP "TRG_busffs"= TNM_dspclk EXCEPT MULTS; # When crossing from dspclk to sysclk using mults delay is not important: TIMESPEC "TS_mults2fast" = FROM "TRG_busnoffs" TO "TNM_sysclk" TS_dspclk; # Crossing from dspclk to sysclk using dffs require maximum setup to minimize metastability: TIMESPEC "TS_bus2fast" = FROM TRG_busffs TO TNM_sysclk 3 ns;
After P&R, trace generates a constraints interaction report which states that some constraint intersection issues exist between sysclk period and TS_mults2fast (but not TS_bus2fast).
However, from the constraints guide "PERIOD is a basic timing constraint and synthesis constraint. A clock period specification checks timing between all synchronous elements within the clock domain as defined in the destination element group. The group may contain paths that pass between clock domains if the clocks are defined as a function of one or the other."
So i think paths coming from mults (clocked by dspclk) should not be included into the sysclk period constraint.
Can you help me to understand whats wrong with the constraints? Or should I simply ignore this section of the constraint report?
A similar constraint intersection exists between the dspclk period and OFFSET IN constraint, and I've always thought the period constraint does not cover paths starting in pads. Am i right?
Regards
Francisco Rodriguez
BTW, I'm using ise 6.2.02i