Hello,

I am trying to specify a timing constraint for a latch that I have in my design. I need to make sure that from the rising edge of the clock to when a control signal goes high that causes the latch to switch, I have less than one clock cycle delay.

This is my UCF file:

####################### ## System level constraints Net CLK TNM_NET = CLK; TIMEGRP "RISING_CLK" = RISING "CLK"; NET "add1_rdy" TPTHRU = "ADD1_RDY"; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC; NET "accumulate" TNM_NET = ACC;

# Constrain CLK to 200 MHz TIMESPEC TS_CLK = PERIOD CLK 5 ns;

# Constrain the accumulate latch (one CLK cycle) TIMESPEC TS_ACC_LATCH = FROM "RISING_CLK" THRU "ADD1_RDY" TO "ACC" TS_CLK * 0.99; #######################

During PAR, I always get the message that the following constraint is ignored: WARNING:Timing:3223 - Timing constraint TS_ACC_LATCH = MAXDELAY FROM TIMEGRP "RISING_CLK" THRU TIMEGRP "ADD1_RDY" TO TIMEGRP "ACC" TS_CLK *

0.99; ignored during timing analysis.Why is that? What is the right way to specify what I'm trying to constraint?

Thanks