I'm using a Xilinx V2Pro part with the 6.2.03i s/w release and I'm seeing the following unconstrained path in the timing report.

================================================================================ Timing constraint: Unconstrained period analysis for net "clk_conv"

Delay: 3.073ns (data path - clock path skew + uncertainty) Source: u0clk_trig_if/trig_conv0 (FF) Destination: u0clk_trig_if/trig_conv1 (FF) Data Path Delay: 3.073ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: clk_conv rising at 0.000ns Destination Clock: clk_conv rising at 2.450ns Clock Uncertainty: 0.000ns

Data Path: u0clk_trig_if/trig_conv0 to u0clk_trig_if/trig_conv1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) -------------------------------------------------

------------------- SLICE_X32Y0.YQ Tcko 0.419 u0clk_trig_if/trig_conv0

u0clk_trig_if/trig_conv0 SLICE_X25Y9.BY net (fanout=2) 2.428 u0clk_trig_if/trig_conv0 SLICE_X25Y9.CLK Tdick 0.226 u0clk_trig_if/trig_conv1

u0clk_trig_if/trig_conv1 -------------------------------------------------

--------------------------- Total 3.073ns (0.645ns logic,

2.428ns route) (21.0% logic, 79.0% route)In my .ucf file, I have set the period on clk_conv, and the report section above shows the proper info on clk_conv. The Verilog code has the registers trig_conv1 and trig_conv0 in the same always block with the proper clock edge. The code seems straight forward.

In another section of the timing report, I see ================================================================================ Timing constraint: TS_clk_conv = PERIOD TIMEGRP "clk_conv" 2.450 nS HIGH 50.000000 % ;

4 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)So it looks like the tools are picking up the constraint, they're just not applying it to these registers.

Any ideas?

Thanks

John Providenza