Timing Analyzer report for IOBs -- 1GSPS DAC interface

Hi,

I'm designing a 1GSPS DAC interface that sends a 500MHz clock and 16bit DDR parallel data in Virtex-5 xc5vlx95t-1ff1136 device.

The 500MHz input clock is driven to a BUFIO that connects to the CLK input of the OSERDES blocks.

This same input clock is driven to a BUFR that divides its frequency by

2 and connects to the CLKDIV input of the OSERDES blocks and the read side of an asynchronous FIFO that holds the data samples.

Each OSERDES output is connected to an IODELAY element and then to a OBUFDS.

I added period constraints for all the clocks in the design into the UCF file and built the code. It passed PAR with 0 timing errors.

In Timing Analyzer tool, I noticed that the 500MHz input clock and its associated BUFIO clock paths were not analyzed, whereas all the FPGA fabric logic that runs @ 250MHz met the timing constraints.

How can I make sure that my design does not have any timing issues at the 500MHz input and BUFIO clocks?

Thanks in advance,

-Pat

PS: Originally posted on X's user forums by ShantM.

Reply to
PatC
Loading thread data ...

there is a sx95t, and a lx85, which is it?

Aust> Hi,

Reply to
austin

It's mispelled. It should read sx95t

Thanks,

-PatC

Reply to
PatC

Pat,

How do you know "it wasn't analyzed" when you also say there is no warning, nor error, and all paths were properly constrained?

One easy way to see if the paths are constrained properly is to tighten the constraint(s) until the tools report those paths do not meet timing.

This is much the same as testing on the bench at higher and higher clock rates until the design fails, but instead you are doing this with the timing tools (rather than testing on the bench).

Always best to use the tools to ensure timing is met, as testing a single device may not provide you with any confidence (that part might be really fast).

Austin

Reply to
austin

Hi,

Here are the UCF constraints I used to do the build

NET "dac_clk_in_p" TNM_NET = dacclk_in_p; NET "dac_clk_in_n" TNM_NET = dacclk_in_n; NET "dac_clk_div" TNM_NET = BUFR_CLK; NET "sys_clk" TNM_NET = sysclk; TIMESPEC TS_dac_clk_in_p = PERIOD dacclk_in_p 2 ns PRIORITY 1; #500MHz TIMESPEC TS_dac_clk_in_n = PERIOD dacclk_in_n 2 ns PRIORITY 1; #500MHz TIMESPEC TS_BUFR_CLK = PERIOD "BUFR_CLK" 4 ns PRIORITY 1; #250MHz TIMESPEC TS_sys_clk = PERIOD sysclk 4 ns PRIORITY 1; #250MHz

The timing analyzer report below lead me to the conclusion that these paths were not analyzed

================================================================================ Timing constraint: TS_dac_clk_in_p = PERIOD TIMEGRP "dacclk_in_p" 2 ns HIGH 50% PRIORITY 1; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected.

--------------------------------------------------------------------------------

================================================================================ Timing constraint: TS_dac_clk_in_n = PERIOD TIMEGRP "dacclk_in_n" 2 ns HIGH 50% PRIORITY 1; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected.

--------------------------------------------------------------------------------

================================================================================ Timing constraint: TS_BUFR_CLK = PERIOD TIMEGRP "BUFR_CLK" 4 ns HIGH

50% PRIORITY 1; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected.

--------------------------------------------------------------------------------

================================================================================ Timing constraint: TS_dac_clk_div = PERIOD TIMEGRP "dac_clk_div" TS_dac_clk_in_p * 2 HIGH 50% PRIORITY 1; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected.

--------------------------------------------------------------------------------

================================================================================ Timing constraint: TS_dac_clk_div_0 = PERIOD TIMEGRP "dac_clk_div_0" TS_dac_clk_in_n * 2 HIGH 50% PRIORITY 1; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected.

--------------------------------------------------------------------------------

================================================================================ Timing constraint: TS_dac_clk_div_1 = PERIOD TIMEGRP "dac_clk_div_1" TS_dac_clk_in_p * 2 HIGH 50% PRIORITY 1; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected.

--------------------------------------------------------------------------------

================================================================================ Timing constraint: TS_dac_clk_div_2 = PERIOD TIMEGRP "dac_clk_div_2" TS_dac_clk_in_n * 2 HIGH 50% PRIORITY 1; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected.

--------------------------------------------------------------------------------

================================================================================ Timing constraint: TS_dac_clk_div_3 = PERIOD TIMEGRP "dac_clk_div_3" TS_dac_clk_in_p * 2 HIGH 50% PRIORITY 1; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected.

--------------------------------------------------------------------------------

================================================================================ Timing constraint: TS_dac_clk_div_4 = PERIOD TIMEGRP "dac_clk_div_4" TS_dac_clk_in_n * 2 HIGH 50% PRIORITY 1; 933 paths analyzed, 367 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum period is 3.613ns.

--------------------------------------------------------------------------------

Thanks, Shant

Reply to
shant.moses

Hi Pat,

I think that the 500MHz clock does not come under timing analysis because there is no fabric logic in this clock domain. Since the only things in this clock domain are hard IP blocks (OSERDES), the synthesis and PAR tools cannot do anything to to affect the timing (bar issue a warning if it detects the clock is too fast or slow). You need to refer to the V5's DC and switching datasheet to ensure correct circuit operation.

Cheers Rob

Reply to
Rob

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