I'm designing a 1GSPS DAC interface that sends a 500MHz clock and 16bit DDR parallel data in Virtex-5 xc5vlx95t-1ff1136 device.
The 500MHz input clock is driven to a BUFIO that connects to the CLK input of the OSERDES blocks.
This same input clock is driven to a BUFR that divides its frequency by
2 and connects to the CLKDIV input of the OSERDES blocks and the read side of an asynchronous FIFO that holds the data samples.
Each OSERDES output is connected to an IODELAY element and then to a OBUFDS.
I added period constraints for all the clocks in the design into the UCF file and built the code. It passed PAR with 0 timing errors.
In Timing Analyzer tool, I noticed that the 500MHz input clock and its associated BUFIO clock paths were not analyzed, whereas all the FPGA fabric logic that runs @ 250MHz met the timing constraints.
How can I make sure that my design does not have any timing issues at the 500MHz input and BUFIO clocks?
Thanks in advance,
-Pat
PS: Originally posted on X's user forums by ShantM.
How do you know "it wasn't analyzed" when you also say there is no warning, nor error, and all paths were properly constrained?
One easy way to see if the paths are constrained properly is to tighten the constraint(s) until the tools report those paths do not meet timing.
This is much the same as testing on the bench at higher and higher clock rates until the design fails, but instead you are doing this with the timing tools (rather than testing on the bench).
Always best to use the tools to ensure timing is met, as testing a single device may not provide you with any confidence (that part might be really fast).
I think that the 500MHz clock does not come under timing analysis because there is no fabric logic in this clock domain. Since the only things in this clock domain are hard IP blocks (OSERDES), the synthesis and PAR tools cannot do anything to to affect the timing (bar issue a warning if it detects the clock is too fast or slow). You need to refer to the V5's DC and switching datasheet to ensure correct circuit operation.
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