Unsupported predefined attribute

Hi, I just got the following error today. I was compiling it yesterday with Xilinx ISE webpack 6.1, and don't know what caused this change. DELAYED attribute is unsupported? Has anyone hit that problem?? The following is the error, and after that is the source. Thanks. ERROR:HDLParsers:1502 - c:/programs/vhdl/ise6/test.vhd Line 14. The    predefined attribute delayed is unsupported tdtfi(vhdl) completed successfully. Release 6.1.01i - spl2sym G.24 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test is   port(in_a: in std_logic; out_a: out std_logic); end test; architecture Behavioral of test is   signal in_a_delay: std_logic; begin   in_a_delay <= in_a'delayed(1 ns);   process(in_a_delay)   begin     out_a <= in_a_delay;   end process; end Behavioral;