I have this:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM; use UNISIM.vcomponents.all;
entity lupicrudi is Port ( clk : in std_logic; clkx2 : out std_logic; clkout : out std_logic); end lupicrudi;
architecture Behavioral of lupicrudi is
signal dummy: std_logic; signal trosky: std_logic;
begin
BUFG_inst : BUFG port map ( O => trosky, -- Clock buffer output I => dummy -- Clock buffer input );
clkx2 4.0, DUTY_CYCLE_CORRECTION => FALSE, FACTORY_JF => X"C080", STARTUP_WAIT => FALSE) port map ( CLK2X => dummy, CLKDV => clkout, CLKFB => trosky, CLKIN => clk, RST => '0' );
end Behavioral;
It doesn't work. clkx2 output is ok but clkout is always high. what is wrong with this source? I use an xc2s50e and ise webpack 6.3.02.
thanks