Do you have a question? Post it now! No Registration Necessary
Subject
- Posted on
Shift register
- 08-30-2003
August 30, 2003, 5:45 pm

Hello!
I am using the WebPack ( VHDL ) and the 9500 family CPLD. I would like
to make a SPI interface. So now I need a VHDL description of an 8 bit
parallel-in serial-out shift register with MSB shifting out first. So
far I haven't had any luck so I am asking you for help. I thank you in
advance for your efforts.
Best regards
George Mercury
I am using the WebPack ( VHDL ) and the 9500 family CPLD. I would like
to make a SPI interface. So now I need a VHDL description of an 8 bit
parallel-in serial-out shift register with MSB shifting out first. So
far I haven't had any luck so I am asking you for help. I thank you in
advance for your efforts.
Best regards
George Mercury

Re: Shift register

You need to do a little work bud. Go to the Xilinx website and read through
some of the application notes. Also, in Webpack, find a menu entry called
"Library Templates". This is FULL of all sorts of examples and templates
you can use. You can even do a Google/Yahoo/whatever search of this
newsgroup and/or the 'net in general and find loads of examples and
tutorials on FPGA's, Verilog, VHDL and other topics.
There's no such thing as a dumb question, but I think that most newsgroup
participants appreciate it when a poster does a little bit of work before
asking for help.
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian
We've slightly trimmed the long signature. Click to see the full one.

Re: Shift register
george snipped-for-privacy@hotmail.com (George) wrote in message

Here's what I cooked up:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- 8-bit load, 1-bit shift out (msb first)

Here's what I cooked up:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- 8-bit load, 1-bit shift out (msb first)
--
-- if load is '1', a new value is loaded from d.
-- if shift_out is '1', next bit is shifted out (msb first).
-- if load is '1', a new value is loaded from d.
-- if shift_out is '1', next bit is shifted out (msb first).
--
entity shft4_1 is
port (d: in std_logic_vector(7 downto 0);
entity shft4_1 is
port (d: in std_logic_vector(7 downto 0);
We've slightly trimmed the long signature. Click to see the full one.
Site Timeline
- » Re: V2Pro, ML300 Linux reference design
- — Next thread in » Field-Programmable Gate Arrays
-
- » DSP
- — Previous thread in » Field-Programmable Gate Arrays
-
- » Fully Comitted to LVDS as Comparitors
- — Newest thread in » Field-Programmable Gate Arrays
-
- » [CHARTER] handvest nl.hobby.elektronica [maandelijks bericht, maart 2021]
- — The site's Newest Thread. Posted in » Electronics (Dutch)
-