Hi,
I'm using the XC95108 CPLD and Xilinx ISE 7.1.01i. The problem I am having is that outputs are inverted when they aren't supposed to be.
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This is my vhdl file:
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---- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test is Port ( In1 : in std_logic; Out1 : out std_logic); end test;
architecture Behavioral of test is
begin Out1