Dear All,
I have a requirement to convert the edge of a clock that the data is valid on. I want to clock data into an entity on the falling edge of a clock and clock data out of an entity on the rising edge of the same clock.
Is the code below sufficient to achieve this functionality? Any pitfalls that I might fall into?
Regards,
Simon
*********************************************** entity clock_edge_conversion is port ( word_stream_out : out std_logic_vector ( 9 downto 0 ); reset : in std_logic; clock : in std_logic; word_stream_in : in std_logic_vector ( 9 downto 0 ) ); end clock_edge_conversion; architecture RTL of clock_edge_conversion is begin process ( clock, reset ) variable temp_word : std_logic_vector( 9 downto 0 ) := B"00" & X"00"; begin if ( clock'event and clock = '0' ) then temp_word := word_stream_in; end if;if ( reset = '0' ) then word_stream_out '0'); elsif ( rx_rocket_io_clock'event and rx_rocket_io_clock = '1' ) then word_stream_out