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What is the best way to clock data in on one clock edge and out on another?

Dear All,

I have a requirement to convert the edge of a clock that the data is valid on. I want to clock data into an entity on the falling edge of a clock and clock data out of an entity on the rising edge of the same clock.

Is the code below sufficient to achieve this functionality? Any pitfalls that I might fall into?

Regards,

Simon

*********************************************** entity clock_edge_conversion is port ( word_stream_out : out std_logic_vector ( 9 downto 0 ); reset : in std_logic; clock : in std_logic; word_stream_in : in std_logic_vector ( 9 downto 0 ) ); end clock_edge_conversion; architecture RTL of clock_edge_conversion is begin process ( clock, reset ) variable temp_word : std_logic_vector( 9 downto 0 ) := B"00" & X"00"; begin if ( clock'event and clock = '0' ) then temp_word := word_stream_in; end if;

if ( reset = '0' ) then word_stream_out '0'); elsif ( rx_rocket_io_clock'event and rx_rocket_io_clock = '1' ) then word_stream_out

Reply to
simon.stockton
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You'll probably have a hard time making it through synthesis. You'll need to...

  1. Break it into two processes, one triggered by the rising edge of clock, the other by the falling edge.
  2. Change 'temp_word' from a variable to a signal so that it can be transferred between the two above mentioned processes.
  3. The 'initial value' that you assign to temp_word is usually not synthesizable. Add an if condition to initialize it to what you want based on the signal 'reset' much like you have for "word_stream_out".
  4. Consider using 'rising_edge(x)' and falling_edge(x) functions that are a part of ieee lib instead of x'event and x = '1'. It's more readable.
  5. I'm assuming that "rx_rocket_io_clock" is a typo and that you meant to say "clock" since there is no signal called "rx_rocket_io_clock"

KJ

Reply to
KJ

KJ schrieb:

The second form is also a simulation mismatch. A transition of x from 'U' to '1' (as it can occur at simulation start) is not a rising edge, but it is an event on x with x = '1'. The same is true for transitions from 'H' to '1' and 'X' to '1'.

Kolja Sulimma

Reply to
Kolja Sulimma

Thanks for the reply,

The code does actulaly synthesis (withouth the typo). However, is it possible that the data on word_stream_out could not be the same as the data on word_stream in, with this current implementation?

If I seperate it into two processes (one on the rising edge and another on the falling edge) and with a temp_word signal between them, will this give me the functionality that I require?

Simon

Reply to
simon.stockton

There is a very simple, albeit wasteful solution: Just cascade two flip-flops. The first one clocked on the falling edge,(usually indicated by a bubble on the clock input), its Q driving a second flip-flop's D, and this second flip-flop is clocked by a rising-edge clock This contraption accepts data right before the falling edge, and outputs the data right after the subsequent rising edge. And the output stays stable until the next rising edge. Ideal behavior. It uses a total of four latches, and runs only at half the conventional clock rate, but it uses conventional circuit elements. Efficiency be damned! Peter Alfke

Reply to
Peter Alfke

I don't know about VHDL, butt something like this in Verilog would probably do the trick:

module xyz(in, out) input in; output out; reg temp;

always @(negedge clock) temp

Reply to
Ron

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