Hi,
I have a question concerning the following phenomenon:
I have a signal which is registered by the following way:
entity xy is port (... DQS : inout std_logic_vector(15 downto 0); ); end xy;
architecture zy of xy is signal l_input_cell : std_logic_vector(15 downto 0); begin
process(Reset, Clk) begin if Reset='1' then l_input_cell '0'); elsif rising_edge(Clk) then l_input_cell
Regards, Allan
ALuPin, First read Allan's post.
Bottom line, if Clk is doing a normal 0-1 transition, these two are equivalent. Highlighting the differences: rising_edge(Clk) finds 0-1, L-1, 0-H, L-H transitions of Clk clk='1' and Clk'event finds all changes except 1-1.
If your problem only occurs at time 0, you have run into a well known issue that is easy to avoid. See below. If this happens at times other than time 0, the clock net is misbehaving and it probably needs to be fixed. I would not consider an X-1 transition of clock a valid functional clock.
From a different point of view, how are you deciding that your designs are different? If you mask out things that occur before reset is applied, are they the same?
Avoiding time 0 Problems
-------------------------- To avoid time 0 problems, I start clock at the inactive edge and I initialize it:
signal Clk : std_logic := '0' ; . . .
Clk
I can't say that the INOUT port would make a difference since you never assign a value to DQS. But there is a difference between the two clock edge descriptions. I don't recall how "rising_edge()" is defined, but it is not the same as "Clk'event and Clk='1'". Even so, I would not expect a difference in how the two operate unless CLK has values other than '1' and '0'.
I belive "Clk'event and Clk='1'" will detect a transistion from *any* value to '1' as a valid clock edge, while "rising_edge(Clk)" requires the previous state to be '0' or possibly 'L'. Does you simulation allow Clk to be undefined with a 'Z', 'U' or 'X'?
-- Rick "rickman" Collins rick.collins@XYarius.com
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