I am looking for some material about the various clock synchronization techniques, their advantages etc.
Thanks Neil
I am looking for some material about the various clock synchronization techniques, their advantages etc.
Thanks Neil
A flipflop does the job. There is little else to be said. You're not talking about a PLL do you ?
Rene
-- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
Not PLL, I am looking at various types of synchronization techniques for signals crossing clock boundaries.
- Neil
Look at the TechXclusives article "Moving Data Across Asynchronous Clock Boundaries"
Click at
Peter Alfke
Neil schrieb:
The following code works pretty reliably, no matter wether the input pulse is shorter or longer than the output domain clock CLK. On each input "event", the output produces a pulse one CLK cycle long.
----------------------------------------------------------------
-- metastable safe spike detector
----------------------------------------------------------------
Library IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY spike IS PORT (reset : IN STD_LOGIC; clk : IN STD_LOGIC; i : IN STD_LOGIC; o : OUT STD_LOGIC); END spike;
ARCHITECTURE rtl OF spike IS
ATTRIBUTE init : STRING;
SIGNAL hold : STD_LOGIC := '0'; ATTRIBUTE init OF hold : SIGNAL IS "0"; SIGNAL edge_d : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL edge : STD_LOGIC; SIGNAL edge_set : STD_LOGIC;
BEGIN
o
Is this the kind of stuff you are after?
Also
HTH.
Regards.
Elder.
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