Clock Synchronization

A flipflop does the job. There is little else to be said. You're not talking about a PLL do you ?

Rene

Not PLL, I am looking at various types of synchronization techniques for signals crossing clock boundaries.

- Neil

Look at the TechXclusives article "Moving Data Across Asynchronous Clock Boundaries"

Click at

Peter Alfke

Neil schrieb:

The following code works pretty reliably, no matter wether the input pulse is shorter or longer than the output domain clock CLK. On each input "event", the output produces a pulse one CLK cycle long.

----------------------------------------------------------------

-- metastable safe spike detector

----------------------------------------------------------------

Library IEEE; USE IEEE.STD_LOGIC_1164.ALL;

ENTITY spike IS PORT (reset : IN STD_LOGIC; clk : IN STD_LOGIC; i : IN STD_LOGIC; o : OUT STD_LOGIC); END spike;

ARCHITECTURE rtl OF spike IS

ATTRIBUTE init : STRING;

SIGNAL hold : STD_LOGIC := '0'; ATTRIBUTE init OF hold : SIGNAL IS "0"; SIGNAL edge_d : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL edge : STD_LOGIC; SIGNAL edge_set : STD_LOGIC;

BEGIN

Is this the kind of stuff you are after?

Also

HTH.

Regards.

Elder.