I want to verify few of my concepts about Processor Local Bus (CoreConnect) in Xilinx FPGA. I know each master on PLB is connected to PLB arbiter on a seperate read and write bus. But i am confused about the shared connection between the PLB slave and PLB arbiter. Is this connection is parallel too. I mean i can see its shared but shared means still 64-bit parallel right ????
17 years ago