clock problems with Spartan 3E starter kit

I'm trying to use the ethernet controller on my starter kit. This chip generates a 25 MHz clock and with every rising edge I have to sample 4 bits of data. First I've tried to synchronize to rising_edge of E_RX_CLK and wrote this for testing:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL;

entity network_test is port( CLK_50MHZ: in std_logic; E_RXD: in unsigned(4 downto 0); E_RX_CLK: in std_logic; E_RX_DV: in std_logic; E_TXD: buffer std_logic_vector(3 downto 0); E_TX_EN: out std_logic; E_MDC: out std_logic; E_MDIO: out std_logic; led: out unsigned(7 downto 0)); end entity network_test;

architecture rtl of network_test is signal main_test: std_logic := '0'; signal rx_test: std_logic := '0'; signal main_counter: natural range 0 to 12500000 := 0; signal rx_counter: natural range 0 to 12500000 := 0;

begin

main_process: process(CLK_50MHZ) begin if rising_edge(CLK_50MHZ) then if main_counter = 0 then main_counter

Reply to
Frank Buss
Loading thread data ...

My USB 8 channel logic analyzer arrived yesterday, so I managed to debug it a bit. With some higher internal clock, generated with a DCM and some latches I managed to sample the 25 MHz data at 100 Mbit and 2.5 MHz data at

10 Mbit (with the same source code). The program saves it to block RAM (which is fast enough according to the datasheet) and outputs it to the RS232 port (as binary data), where I was able to read the MAC address of my Windows PC, which sends broadcast packages from time to time.

I've tried to implement the RS232 interface as Whishbone components, but I'm not sure about the signals and timings. Is it true that the master has to wait for ack=0 before it can signal another stb=1?

Below is the new source. Please comment it, if there are some things which can be simplified or which can cause timing problems, because this is my first bigger FPGA project and I'm not always sure how and when signals are propagated and sampled.

Now I'll try to add the sending part and then some higher layers, like the DHCP client protocol and maybe finally a simple web server. I'll post this in the comp.lang.vhdl newsgroup for discussion and bugfixing for adding it to the Spartan 3E design examples site (

formatting link
).

-- rs232 sender with whishbone slave interface library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.MATH_REAL.ALL;

entity rs232_sender is generic(system_speed, baudrate: integer); port( ack_o: out std_logic; clk_i: in std_logic; dat_i: in unsigned(7 downto 0); rst_i: in std_logic; stb_i: in std_logic; tx: out std_logic); end entity rs232_sender;

architecture rtl of rs232_sender is constant max_counter: natural := system_speed / baudrate; type state_type is ( wait_for_strobe, send_start_bit, send_bits, send_stop_bit);

signal state: state_type := wait_for_strobe;

signal baudrate_counter: natural range 0 to max_counter := 0; signal bit_counter: natural range 0 to 7 := 0; signal shift_register: unsigned(7 downto 0) := (others => '0'); signal data_sending_started: std_logic := '0';

begin

-- acknowledge, when sending process was started ack_o

Reply to
Frank Buss

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.