Change clock domain for FIFO ...

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Hi,

I have to introduce a DVB Trasnport Stream (Clk + Data + Sync) from a tuner
in a fpga. Fpga has a 27 MHz clock with which takes data from the tuner and
serializes them to ASI. The serialization works well simulating a Null
Packet as input.

Now I have to take data from the tuner with unknown clock. I had thought of
a async FIFO. The clock of the tuner to the left of fifo, to the right my
clock. Checking the level of fifo and inserting Null packet if necessary.

But how can clocking the fifo directly by the tuner without problems ?

Do you have an example of VHDL code that I could use ?

Thanks.

Kappa.



Re: Change clock domain for FIFO ...
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That sounds quite reasonable as this is a typical usage of a fifo
(switching between clock domains).

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 > Do you have an example of VHDL code that I could use ?

Well depending on the device you use there might be some small hacks to
think of (e.g. Virtex-4 BRAMs in FIFO mode need at least 3 cycles of the
slowest clock to do a reset). Nevertheless both of the two major FPGA
vendors offer quite stable implementations for FIFOs. So what exactly
are You looking for?

Anyway what do You mean with "unknown clock"? Does the frequency vary
while in use or is the clock stable for a type of tuner and another
tuner has a different frequency? What about the jitter of the clock?

Regards,

Lorenz

Re: Change clock domain for FIFO ...
Thanks Lorenz,

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I use a Virtex-4 SX35 and Spartan-3E 500 ...

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Exactly. The clock input can vary from a minimum of 125 Hz to a
maximum of 11250000 Hz. Some problem could be the first to power up.

Any idea ?

Regards,

Kappa





Re: Change clock domain for FIFO ...

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Well, I'd give it a try and directly connect that clock on the producer
(write-) side of the FIFO. Only if that does not work (though I think it
will) You should consider sampling the data yourself using a clock with
at least 22500000 Hz, but I'd not recommand that, as sampling might
really bring You some unexpected results.
Nevertheless if you have to: I'd design some kind of "edge detection"
for the input clock (saving the last value and comparing it to the
current value) and sampling then whenever you detect an edge.
You might also want to consider sampling only with falling edge
depending on when the data is stable compared to the clock's edges

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Regards,

Lorenz

Re: Change clock domain for FIFO ...
Hi Lorenz,

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I have 27 MHz, Do you think it is enough ?

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This code is right ?

[code]
entity parallel_input is
 port (
            reset        : in
            -- External reste
            clk           : in
            -- Clock 27 MHz
            clk_tuner : in  std_logic;                                    --  
Clock tuner (depends on Symbol rate)
            din          : in  std_logic_vector (7 downto 0);    -- Parallel
Transport stream
            sync        : in
            -- Sync   (1 = Sync / 0 = Data) (0x47) on Transport Stream
            parity       : in
            -- Parity (1 = Data / 0 = Parity)            on Transport Stream
            dout         : out std_logic_vector (9 downto 0);  -- Output for
fifo (D/P + Sync + Data)
            vout         : out
          -- Valid out for WE FIFO
       );
end parallel_input;

architecture Behavioral of parallel_input is

 --
 -- Internal Signal
 --
 signal syncExClock : std_logic := '0';
 signal lastExClock : std_logic := '0';

begin

 -- Capture Clock
 process(reset, clk)
    begin

        if reset = '1' then
            syncExClock <= '0';
            lastExClock <= '0';
           dout <= (others => '0');
       elsif rising_edge(clk) then
           syncExClock <= clk_tuner;
           lastExClock <= syncExClock;
           dout <= parity & sync & din;
       end if;
 end process;

 -- Output
 vout <= syncExClock and not lastExClock;

end Behavioral;
[/code]

Regards,

Kappa.



Re: Change clock domain for FIFO ...

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This is sort of a text book example. The easiest way though is to
clock the FIFO at the highest frequency and create clock domain
transfer logic at the interface with the lowest frequency. This way
you keep your FIFO at one clock frequency and put the tricky part in a
relative simple piece of logic.


--
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

Re: Change clock domain for FIFO ...
Hi,

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I am okay. Sample with my clock against the rising clock of tuner and
this enabled the writing of FIFO ?

Some code ?

Regards,

Kappa.

Re: Change clock domain for FIFO ...

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1. Search the web site of whatever vendor you plan to implement this in for
a dual clock fifo.
2. Instantiate that component

Alternatively, google for
- lpm_fifo_dc (dual clock fifo) and you should be able to run across the
source code.  Altera's code is in a file called 220model.vhd which you get
with Quartus.
- Opencores.org probably has something
- 'dual clock fifo' will probably have some hits as well.

It's not hard, do some research.

KJ



Re: Change clock domain for FIFO ...
Thanks KJ,

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I do not search 'dual clock fifo', thanks. But i search a interface
code for place a external clock + data to 'dual clock fifo' for first
domain clock. The dual clock fifo is ready. I still want to link the
'Tuner'.

Regards,

Kappa.


Re: Change clock domain for FIFO ...
A dual-clock (also called asynchronous FIFO) is complex inside because
of the flag control, but is very easy to use:
The input port and the output port are completely separate. You put in
data at any rate, and you pull it out at any other rare you desire.
There is a Full flag that tells you tonstop writing into it, and there
is an Empty flag that tells you to stop reding from it. End of story.
It acts like the waiting room at the doctor's office...
Peter Alfke

Re: Change clock domain for FIFO ...
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I'm not sure what your application is, but for DVB-ASI you might also
want to make sure that you do any PCR restamping, if needed, on the
appropriate side of the FIFO. If you blindly dump your data into some
clock-crossing FIFO you'll wind up introducing extra PCR accuracy
jitter.

 - Kenn

Re: Change clock domain for FIFO ...
Hi Kenn,

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It's true, his problem will be solved later, for now is fine as is. Thank.

My problem remains take data from the tuner and place in fifo, without
problems of any kind.

Regards,

Kappa.



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