DDR DIMM clock distribution

Hi

I'm using Cyclone II EP2C8 in PQFP208 package and DDR DIMM. And I'm wondering how to distribute clock signal. DIMM has 6 clock signals (3 differential pairs). I figure out two solution:

1. Use differential output PLL_OUT and split signals to three DIMM input.

1. Use 6 general purpose FPGA IO to distribute three pairs of clock and shifted clock. (This IO pins will be single-ended not differential)

Which soulution is better and will have lower skew to other DDR signals? Or maybe do that on different way?