maybe you folks can help me with a design decision:
I need to distribute a clock to up to ten identical boards. The boards are all plugged into a backplane in a single row.
In addition to the backplane the boards will be connected by a twinax flatband cable on samtec connectors. For the clock distribution I can choose between a bus structure cable or a series of point to point connections between neighbouring boards.
The leftmost of the identical boards shall provide a clock for all the other boards. I am now concerned that a bus structure with that many stubs will have problems maintaining a good signal quality.
I could instead use point to point connections with fanout clock buffers on each board to forward the clock to the next board. As far as the signal quality goes this will obviously work very well, BUT the boards need a fixed phase relationship. While the absolute phase is of no importance, the phase must not drift over time or temperature by more than 50ps or so. Ten buffers in a row would probably have a larger drift, wouldn't they?
Any ideas, how I can make a pure passive distribution work in a setup like that?
Also: How can I turn on the termination on the last board dynamically?
I would generate the clock on the center board, then fan out in both directions and terminate on both ends, which of course means that the driver sees half the characteristic impedance... Peter Alfke
Have you considered using a clock buffer on the backplane? By using point-to-point connections, your design is significantly cleaner but you no longer have a passive-only backplane solution.
1) What frequency is the clock? The higher the frequency, the more likely you are to have problems with reflections from an edge during the next edge.
2) What is the rise time of the clock? The faster the rise time, the bigger the reflections, in general.
3) What logic standard is the clock?
4) What does the clock drive on the destination cards? FPGAs have relatively large pin capacitance which can cause big reflections at fast edge rates.
Your 50ps requirement rules out any tricks with DCMs, they have that much phase noise and more already.
I like your daisy chain plan. As you are worried about 50ps, this must be the safest way to go. You could use something like the SY58011u 1:2 CML buffer from Micrel, depending on your operating temperature range. The datasheet has a graph of propagation delay versus temperature. From 10C to
80C the delay changes by 10ps more or less linearly. If you can keep the temperature range low, this might be ok. Use one output to drive the board, the other to drive the next board. They also make 1:4 parts, so the first board could drive the next 3, the 4th drives 5,6,7 and so on. So you'd have fewer buffers.
I hate to say it, but why do you wish to architect a system that has this requirement? Why not solve the problem in a way that does not require this 50ps phase alignment? The added FIFO buffering may be well worth the pain of precise clock phase control/signal integrity.
You could distribute some slow clock and generate your fast clocks on each board independently with high quality PLLs but that's not a pure passive solution you've asked for...
That is a simple question: It is a device to measure the timing of input signals. We have 25ps resolution now and want to improve on that. The problem ist that we can only fit 8 inputs on any board. Most customers need only less than 8 channels, but some need a lot more. These are important customers, but the volume is really low, so we would rather use a standard backplane with our standard boards.
That is OK. We definitely will have jitter cleanup PLLs on the boards. I am not looking for a passive solution because I want a simple or cheap solution, but because I am worried by the temperature dependant delay of the active components.
And otherwise you think I can get a clean enough edge across 10 stubs? (or 5 using Peters suggestion). The setup is rather complex for a simulation.
r
Well, fast risetimes is a way to reduce phase shifts due to variations in threshold and supply voltage. So currently I am looking into very fast rise times.
Free to choose. I am looking at CML and LVDS currently.
ly
Good point, I did not think of that. Maybe external clock buffers on the inputs could improve on that.
Even external zero delay buffers often have something like 200ps skew.
,
e
That is a great suggestion. I had a look at multiple parts but only one of those specified the temperature effect - which was to big. 10ps over 70=B0C is rather good. The linear solution has the advantage that it is easy to make all boards identical.
*sigh* It's a big task for simulation. But I probably will have to.
That would work, but than we need custom made backplanes. An intermediate solution is to have one special board that provides ten clock lines and then shifting the clock lines by one on each board. Of course this clogges 20 lines on the cable.
Well, jitter cleanup is not what I am talking about. Take for example 10 MHz as your base clock (actually sinewave might be preferable because of better phase noise) and generate whatever your want on each of your boards with high-precision PLLs. You can even synchronize them all with a bussed signal.
I don't know how cheap you can make it with requirements in picoseconds...
Since you're looking at precision timing requirements, you will have issues. Considering that 50ps is about a half centimeter of propagation delay on a PC board, you're already at a loss.
If all you want is 50ps of repeatability (and account for the propagation delay as a fixed offset per board), your situation is better but still poor. If you use a standard backplane, do you really believe you can maintain fidelity going backplane to card to backplane to card to backplane to card.... If you had ideal terminations, with ideal connectors, you could achieve your goal. The impedance issues you have traveling through the connectors is probably enough to change the timing of the 2nd card depending on whether the 3rd or 4th (or
10th) cards are plugged in even with appropriate terminations.
Buffering is also a problem since every buffer is going to add some noise. With a multiple-output clock buffer, you're still looking at channel matching as an issue.
So, consider wandering off to the RF realm. Generate a sinusoidal high-frequency clock. Rather than using a full level signal you can passively split the sinusoid into your desired number of channels at the source or on the backplane and terminate each clock *on the backplane* and use an impedance-matched front end on your cards so they *look* like open circuits to the backplane traces. Alternatively, use one backplane-terminated trace for the sinusoidal clock and do a better job of making the cards look like open circuits to the buffers. In either case, you have added noise from the clock receive buffer on each card.
If your cards are identical, you probably want a way to shut off the unused clocks on each destination card.
Each card will have an offset from the first card based on the propagation delay across the backplane. The first card will have a different offset still since its clock is received before launching onto the backplane.
You have a pretty strenuous requirement but you can eliminate many of the troubles by getting rid of reflections and tuning the receivers to look like open circuits.
I once made a power splitter for a 155 MHz sinusoid by using 1-ft lengths of coax and T-connectors. Since two 50-ohm terminated cables teed together look like 25 ohms and 25 ohms across a 50 ohm, quarter wavelength cable looks like 100 ohms to the other side, 2 of these pairs look like 50 ohms when teed together. When properly terminated, each signal was 1/4 power. When I looked at one of the channels on a scope and removed one of the other terminations, the scope signal didn't get larger, it got smaller! It was fun to show people and have them scratch their heads over the situation. I had clean sinusoids in, clean sinusoids out, and used standard RF techniques to deal with stubs and impedances. Fun stuff.
That would be OK. I only need repeatability over time and temperature. Different setups can have different skews. Even two identical setups can have different skews. The skew only leads to a shift of the resulting image. That can be calibrated (or even ignored in many cases) But if I start accumlating an image today and run the experiment for a week any shift in skew during that time will smear the image.
A standing wave came up during discussion here. The problem is, that this is very difficult for varying number of boards. I would rather not stock ten completely different, length matched cable setups.
=46rom your original post, it didn't seem that running individual traces from board #1 to each of the other boards was an architectural option for whatever reason, but if it is and you get a beefy enough set of drivers on the board then series terminate the clock. That will distribute the clock signal passively without accumulating any time/ voltage skew caused by the distribution itself (the driver and receivers will still have some) and will have good signal quality at each receiver.
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