V5 LXT PCIe Block simulation

I am trying to simulate PCI Express Endpoint Block 1.1 generated by coregen in ModelSim SE. I get the following errors

Error: ../../src/pcie_top.v(2153): Module 'PCIE_EP' is not defined Error: ../../test_bench/pcie_ne.v(1221): Module 'PCIE_INTERNAL_1_1' is not defined

I have Installed the following as per Answer Record 9795 ISE 8.2, service pack (8_2_03i_lin.zip), IP update 2_3 (ise_82i_ip_update2_3.zip), Virtex-5 LXT Device (8_2_03i_v5_lx330_lxt.zip) and IP Update 2 LXT supplement 1_1 (ise_82i_ip_update2_lxt_sup_1.zip)

Also I have installed all the smartmodels from the following two locations $XILINX/smartmodel/lin/image and $XILINX/virtex5/smartmodel/lin/image

Following are the models in my library ======================================== For platform: x86_linux ========================================

======================================== Report of all versions of all models in the Library: ========================================

model: dcc_fpgacore_swift versions: 02402 model: emac_swift versions: 01022 model: glogic_adv_swift versions: 01004 model: glogic_swift versions: 04001 model: gt10_swift versions: 02221 model: gt11_swift versions: 01016 model: gt_swift versions: 01602 model: gtp_dual_swift versions: 00008 model: pcie_internal_1_1_swift versions: 00017 model: ppc405_adv_swift versions: 01010 model: ppc405_swift versions: 04003 model: temac_swift versions: 00002

Am I missing any thing I need?

-Sovan