Folks, I need to do a trial synthesis to see if one of our ASIC design module will run at speed (~312.5Mhz) in Xilinx Virtex 5 LXT fpga. Is SYnplify Premiere the front end synthesis tool to use for this exercise ?
--Chirag Shroff Tech Lead GGSG Engineering Cisco Systems
The question your're asking is a bit like "how long is this bit of string". All of the Physical synthesis tools claim better performance and from what I have seen there is some truth in those claims. However how far it goes is ultimately limited by the design entered by the human and usually it's is the human being's best efforts that determine if that speed is attained. The speed that you are looking to attain is possible in V5 but only if the design does not have too many logic levels between flip-flops etc. etc.. Best way forward is simply to try it and see how bad a timing result you get before entering the game of making timing closure.
John Adair Enterpo> Folks,
John,
I agree. It's a little bit of an open ended question. I guess, I was looking for someone to jump in and say, try this particular tool because it did the trick for us.
BTW, I did try Synplify Premiere and I am close to 270Mhz with just the tool "switches".
--Chirag Shroff > The question your're asking is a bit like "how long is this bit of
Did you run it through the ISE backend tools as well? Synplify can be very optimistic in its estimate of net delays.
ah
With a name like Cisco I would set up an NDA with Synplicity and Mentor (Precision Physical) give them the design and say hey I need 312.5MHz and if you can achieve it I will buy it :-)
Hans
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