I've got a question regarding clocks and jitter. Let's say I have 2 ADCs that need an input clock of 80 MHz. have an 80 MHz low-jitter crystal connected to an FPGA and then I use the FPGA as a clock buffer and I output the 2 clocks from the FPGA to the 2 ADCs.
We know that clock jitter is critical for high-speed ADCs, so I would like to know, is it a good way to distribute a clock to two ADCs? Will the FPGA add jitter? Assume I do not use any PLL in my design, the clock goes straight from the input pin to the 2 output pins on global routing resources. I've looked at Altera datasheet and it is not really clear what jitter would be added by the FPGA, the only place jitter is mentionned is for PLLs not for clock routing.