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Clock distribution for ADC and jitter

Hi everyone,

I've got a question regarding clocks and jitter. Let's say I have 2 ADCs that need an input clock of 80 MHz. have an 80 MHz low-jitter crystal connected to an FPGA and then I use the FPGA as a clock buffer and I output the 2 clocks from the FPGA to the 2 ADCs.

We know that clock jitter is critical for high-speed ADCs, so I would like to know, is it a good way to distribute a clock to two ADCs? Will the FPGA add jitter? Assume I do not use any PLL in my design, the clock goes straight from the input pin to the 2 output pins on global routing resources. I've looked at Altera datasheet and it is not really clear what jitter would be added by the FPGA, the only place jitter is mentionned is for PLLs not for clock routing.

Thanks

Reply to
Benjamin Couillard
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The quality of the ADC sampling will be better if you distribute the clock from the original 80 MHz source to both ADCs and the FPGA with a dedicated clock buffer.

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

I was once in a communications circuit seminar with a bunch of FPGA types and I asked some question about doing something that depended on the FPGA clocking being low jitter -- I got laughed at.

Since then I've remembered that whenever I needed to depend on clocks remaining pristine as the wend their ways through FPGA logic.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com
Reply to
Tim Wescott

I'd expect troubles from noise on the power rails if the FPGA is running other logic. How good/bad are they if they are only acting as a clock switcher/divider?

--
These are my opinions, not necessarily my employer's.  I hate spam.
Reply to
Hal Murray

Thank you both for your answers.

I'll put a dedicated clock buffer!

Reply to
Benjamin Couillard

Though not a comment on jitter per se, most FPGA architectures do not support directly connecting a global net to an output; they usually have to go through some amount of local routing to get from the global net to the output. The choice of local routing resources (and therefore propagation/skew between multiple outputs) is dependent upon what other signals are competing for those resources. You can try to manually route them, and lock that down (ugly), but I have run into issues where the same routing paths and delays from the global net to the output (input of the output buffer) were not present on each output.

One solution to this output skew problem is to use two DDR output FFs, both clocked from the global clock net, and hard-wired to '1' on the rising edge data input and '0' on the falling edge data input. You may need attributes or have to instantiate the DDR primitive to keep synthesis from trying to optimize it out. This way you are using dedicated global routing to get to the output FF, and dedicated circuitry from there to the pad, resulting in predictable, repeatable delay and skew between outputs.

Like I said, this does not do anything (good) for jitter, but it does solve skew problems, at least in a predictable, repeatable way.

Andy

Reply to
Andy

This is all true, but the question is jitter. If you only have one ADC, then skew isn't usually a problem. Jitter can be.

I haven't seen so much discussion on sources of jitter within the FPGA, or how it compares to other methods.

-- glen

Reply to
glen herrmannsfeldt

,

The OP stated he had 2 ADCs. Skew can be a problem with 2 ADCs, depending upon the application.

Andy

Reply to
Andy

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