have some small program:
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dek_zak2 IS PORT (Zegar,Jesli11,Jesli13: IN std_logic; Wyjscie : OUT std_logic); END;
architecture Behavioral of dek_zak2 is signal wartosc : integer range -3 to 12; signal nastepny : integer range -3 to 4; begin
dek_zak2 : process (Zegar,Jesli11,Jesli13)
begin if Zegar'event and Zegar = '1' then if wartosc = 11 then wartosc
Think of how you would take a positive edge triggered flip-flop and wire it up to achieve your goals. Using multiple clocks to trigger a single register isn't a good synchronous design approach. If you're trying to do an up/down counter triggered by other (slow) events, consider running your system with a master clock and provide a single up/down *enable* pulse per up/down event.
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Ygh ?? Im litle bit new to vhdl. Ive tried to test having only one 'if' with event (first one) and two "ifs" normal: if Jesli11 = '0' ... but it doesnt change anything.
If you know nothing about hardware, you won't be able to code with VHDL. One of the basic building blocks of hardware is a register, or "flip-flop." This is a storage element that takes the data that was available on the input at (typically) the rising edge of the clock and transfers that value to the output. It is a very well defined piece of hardware that the HDLs have been designed to use. Your code will eventually be mapped to these storage elements and cannot be randomly combined. As a processor's line of assembly code has a mnemonic with specific parameters that apply for that mnemonic, so to does the hardware have specific building-blocks that can have only a preset combination of inputs and outputs.
First try a simple up counter. Nothing fancy. I'd suspect you'll design with the up signal clocking the counter.
Second, try to use a steady frequency to clock your counter on continuous clock edges with a one-pulse-wide enable when you want to count up.
Third, extend the logic to have an up enable and a down enable to get your counter moving in the right direction, one tick at a time.
Learning hardware is NOT something to do with code, it's something to do by understanding the function of the elements the HDL has to work with and writing the HDL to properly manipulate those pieces. Once you understand what the limits are of the hardware, synthesizable code should come easier.
Signals below are signed. Consider using STD_LOGIC_SIGNED or NUMERIC_STD packages.
"if rising_edge(X)" is (AFAIK) indistinguishable from "if X'event and X='1'" both tell the synthesizer that X is the clock to registered quantities described inside the if clause. If Jesli11 is a synchronous variable common practice would be to hold it in a register
if rising_edge(clk) then Jesli11previous if wartosc < 11 then wartosc else nastepny end if;
Especially for beginners I would recommend _always_ defining the else clause for an if clause. Specify what you want nastepny to do when the "if" is true and what you want wartosc to do when the "if" is false.
Here you have two separate if clauses defining the same variables. This is legal but not recommended. What behavior do you want when both "if"s are true
-- rising_edge(Jesli11), rising_edge(Jesli13) -- what behavior when neither is true ? Consider using "elsif" and "case" statements.
Hope this helps,
-rajeev-
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