i2c-core from opencores.org

I'm trying to use the i2c-core from opencores.org. I made a project in Altera Quartus II and added the 3 VHDL-Files. Compiling is no problem, but I have problems with the simulation. I'm doing: 1) reseting the core 2) write clock prescaler (Addr 0 and 1) 3) enable core in control register (10000000 to Addr 2) 4) write data for writing to slave to transmit register (Addr 3) 5) start and write to command register (10010000 to Addr 4) and nothing happens on the output-lines !!!??? Reading the status register (Addr 4) shows 'Transfer in Progress' every time! What i am doing wrong ??? Can someone help ? Thanks, Manfred

Reply to
Manfred Balik
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Forgot the pull ups on the i2c lines so the controller waits for the bus to become inactive?

Regards Thomas

Reply to
Thomas Rudloff

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