switching problem

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I'm trying to build the following thing: a 7-segment-led that increases its
value every time a switch is pressed.

library IEEE;

entity sevsegment is
    Port (
    clk_i: in std_logic;
    sevseg : out std_logic_vector(6 downto 0);
           reset : in std_logic;
     switch: in std_logic);
end sevsegment;

architecture Behavioral of sevsegment is
signal sevseg_s: std_logic_vector(6 downto 0);

variable counter: integer range 0 to 9;
 if clk_i'event and clk_i='1' then
   if reset='0' then
        sevseg_s <= "1111110";
  elsif switch'event and switch='0' then
      if counter<9 then
      end if;
  case counter is
   when 0 => sevseg_s <= "1111110";
   when 1 => sevseg_s <= "0110000";
   when 2 => sevseg_s <= "1101101";
   when 3 => sevseg_s <= "1111001";
   when 4 => sevseg_s <= "0110011";
   when 5 => sevseg_s <= "1011011";
   when 6 => sevseg_s <= "1011111";
   when 7 => sevseg_s <= "1110000";
   when 8 => sevseg_s <= "1111111";
   when 9 => sevseg_s <= "1111011";
  end case;
end if;
end process;

sevseg <= sevseg_s;

end Behavioral;

Why doesn't it work? I know that "multiple clocks" are not allowed, but i
can't find any solution to solve my problem.... :-(((((((((
In the end, everything should be implemented to a spartanII-FPGA...

Thank you very much,

Re: Switching problem


When you say, "Why doesn't it work?" it would be
helpful to know what the failure mechanism is...

I wonder if this is a lab assignment gone wrong,
or an astute application of reverse psychology
to get an answer to a homework question?  ;)

For what it's worth, I think you might go back
and review how to describe a synchronous counter.
Your code may simulate properly, but a synthesis
tool may have a difficult time implementing it.

You could design a synchronous counter with no
clock enable, where the switch signal is used as
the clock, assuming you debounce it properly.

Or, you could design a synchronous counter that
is clocked from a free-running clock, and you use
the switch signal as a clock enable, assuming
you debounce and synchronize it properly, and
then detect transitions on the signal across
clock cycles to generate a single "press" event
that will allow the counter to increment only
one time in response.


Simone Winkler wrote:
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Re: switching problem
Hi Simone -
  As Eric suggested, there is code which simulates, but might not be
synthesizeable.  One problem area might be the use of multiple clocks.
   Switch does not need to be a clock in this case.  The starting point
would be to build a simple edge detect circuit for a normally HI signal,
with low going pulse for an event capture.

  q0_switch <= switch;             [clocked with clk_i]
  q1_switch <= q0_switch;      [clocked with clk_i]
  switch_leading_edge_detect = ~q0_switch & q1_switch.  [combinational]

  Then you can use switch leading_edge_detect in place of the switch'event
switch = 1'b0;

  Problem with above is that both the leading and trailing edges of the
are typically noisy, and debouncing switch signal is required.  Logic here
be to generate a stable_hi signal which is set HI on reset.  When the switch
is low for 50 consecutive 1 msec samples, then stable_hi can be cleared.
switch in is high for 50 consecutive samples, it can be set hi again.

  Last problem is that you need a default condition defining sevseg_s for
counter values not specified in case statement.

  Good luck.

John Retta

email : jretta@rtc-inc.com
web :  www.rtc-inc.com

----- Original Message -----
Newsgroups: comp.arch.fpga
Sent: Friday, September 05, 2003 1:59 PM
Subject: switching problem

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