EDIF generation from Verilog in ISE 6.2i

Dear All,

I wanna generate EDIF netlist from Verilog code. I am using Xilinx ISE6.2i software, and cannot find any trace of EDIF netlist generated.

PS. The code synthesizes OK.

Reply to
apai
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I don't think XST can generate EDIF anymore. If you want EDIF you need to use a third party synthesis tool like DC-FPGA.

Petter

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Reply to
Petter Gustad

XST produces a .ngc file, which can be converted to EDIF with ngc2edif.exe. You can then convert the EDIF to a .ngd file using edif2ngd.exe.

(I have noticed discrepancies between the ngc and the edif related to attributes, so beware.)

Regards, Allan

Reply to
Allan Herriman

As I said earlier, I think they have removed this functionality. In ISE 6.2i SP3 you get the following message if you try to run ngd2edif:

"The ngd2edif program and generation of back-end EDIF netlist for simulation is no longer supported in the current software. Please use netgen program to generate Verilog or VHDL netlists for simulation."

Petter

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Reply to
Petter Gustad

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