Dear All,
I wanna generate EDIF netlist from Verilog code. I am using Xilinx ISE6.2i software, and cannot find any trace of EDIF netlist generated.
PS. The code synthesizes OK.
EDIF generation from Verilog in ISE 6.2i
Sep 08, 2004
3 Replies
I don't think XST can generate EDIF anymore. If you want EDIF you need to use a third party synthesis tool like DC-FPGA.
Petter
A: Because it messes up the order in which people normally read text.
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XST produces a .ngc file, which can be converted to EDIF with ngc2edif.exe. You can then convert the EDIF to a .ngd file using edif2ngd.exe.
(I have noticed discrepancies between the ngc and the edif related to attributes, so beware.)
Regards, Allan
As I said earlier, I think they have removed this functionality. In ISE 6.2i SP3 you get the following message if you try to run ngd2edif:
"The ngd2edif program and generation of back-end EDIF netlist for simulation is no longer supported in the current software. Please use netgen program to generate Verilog or VHDL netlists for simulation."
Petter
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
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