VHDL code for Generating registers

Some queries are trivially easy....

process(Clock) begin if rising_edge(Clock) then My_Register_Signal

Many people will recommend Peter J. Asheden's book "The Designer's Guide to VHDL (2nd edition)", It was my first VHDL book and it was too overwhelming for me to read at the time. However, it's been a usefull reference book. At least a third of the book describes the author's CPU.

Sundar Rajan's "Essential VHDL RTL Synthesis Done Right" used to be my favorite VHDL book. It keeps things simple, explains a lot about the VHDL code examples, and shows logic diagrams that a synthesis tool produces from each example. It does get into state machines, including a simple PCI bus state machine. However, it's very weak on simulating and debugging. And unlike many other VHDL books, there isn't code for a CPU!

Pong P. Chu's "RTL Hardware Design Using VHDL" is now my favorite VHDL book. This is somewhat like Rajan's book, but Chu's book goes into more detail and covers a lot more topics, including Meally & Moore state-machines, clock synchronizing, and even sending info across clock domains. Like Rajan's book, this book also includes logic diagrams for the code examples. I think that this book would be ideal for a beginner. It's only assumption it that the reader already knows digital logic fundamentals. Its only flaws are a) the book's index is poor, b) when code is continued on the next page, and when there's a diagram on the next page for a new topic, the continued code comes after the diagram. This can be a little confusing.

HTH

-Dave Pollum