explain the vhdl code

hi to all can anyone please explain to me how each line of the code work please..... thank to all :)

library IEEE; USE ieee.std_logic_1164.ALL; ENTITY dte IS PORT ( rst,dcr,ri,cd,cts,rxd,data,clk: in std_logic; dtr,start,rts,txd,out_dte: out std_logic); END dte; ARCHITECTURE dte_arch OF dte IS TYPE state IS (st0,st1,st2,st3,st4,st5,st6,st7,st8,st9, st10,st11,st12,st13,st14,st15,st16,st17,st18,st19, st20,st21,st22,st23,st24,st25,st26,st27,st28,st29); SIGNAL present_dte,next_dte:STATE; BEGIN processdte: PROCESS (rst,dcr,ri,cd,cts,rxd,data,clk) BEGIN if rst='0' then present_dte

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EVERY LINE?!!!!

In general terms, out of respect for those who might take time away from their work to help out on a newsgroup, it is customary to at least make an attempt to exhaust generally available sources of information FIRST and only then resort to posting on a newsgroup.

There are many freely available VHDL tutorials on the Web. Do a search for such topics as "VHDL", "VHDL Tutorial", "FPGA Tutorial", "HDL Tutorial", etc. Get creative. Spend a week trying to learn and figure this out on your own. If you have specific questions I'm sure many here would be glad to help you.

Hi, Thats a sequential 30 state state machine.Depending on the value of presetn_dte it selects one of the cases and does the specified operation.

get any VHDL book, look for modelling a state machine. or refer to Digital system desing using VHDL by charles H.Roth. chapter 2. The program uses a case statement eg, let a be a one bit signal, so when a == '1' it does some operation or when a == '2' it does diff operation. code: case a is when '1' => when '2' => end case;

bye RAm

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