Chipscope Pro and VHDL

ChipScope Pro generate some sort of VHDL block that you place in your design and connect the appropriate signals to?

this, pleas elet me know. Thanks

not quite but close, CS core gen generates edif files that you can use in verilog vhdl or schematics core inserter insertst the cores directly to netlist so you would not see them at all.

coregen generates example files that provide the template you must use to access the cores. you need to connect the control port(s) from icon to all the actual cores and connect the signals and clock thats it

antti ebook.openchip.org