Xilinx registers resetr value

Hi all.

I am working with the Xilinx xcv300e and I was told that if I do not assign a reset value to registers they will be set to 0 when the device is programmed, so there must be an implicit global reset. Now I noticed that in the vhdl model generated both by the XPS and ICE for simulation purposes some of the instantiated registers without an explicit reset state in the vhdl source code are set to 1 and other are set to 0 and this facts has a big impact on the logic because the initial state of the device is different from the one it was supposed to be in.

Does anyone know how to solve this problem? Is it only a difference between the simulation models and the real device? How the Xilinx tools decide which registers have to be reset and which register have to be set at startup?

Thanks in advance,

Andrea