I need to design an FPGA for a chip bringup system with the following clocking requirements:
There is a 2.75 MHz input clock from the DUT. One part of the FPGA-DUT interface is running on this clock. We need to generate a 11 MHz ( 4x) clock using the 2.75 MHz input. One part of the FPGA-DUT interface is running on this 4x clock.
Given the slow speeds involved, I dont need a phase-lock. There is large timing margin. But I need the FX functionality in the DCM to generate the higher frequency clock. I am planning to get a 16x ( 44 MHz ) clock generated at the FX output of the DCM and then divide using a simple counter to get the 4x clock.
How to I connect the feedback clock input of the DCM? For other designs where the input clock frequency is high enough for DLL locking, we take the CLK0 through a BUFG and connect it back to CLKFB. The same signal also goes to the flops in the design.
Thanks.
-Dipu