State Machine and Area Estimate Question

Hi, I have a design with 2 components, each of which implement a small but non trivial state machine. Each one has an associated area estimate reported by Xilinx, say A1 and A2. Now I realized that both of these components would never execute their state machine concurrently so I combined both state machines into one larger state machine, with the idea that I might be able to save some area since states in both individual state machine might use the same resource. At the very least I thought the new area of the larger state machine would be A1 + A2. I was actually expecting something smaller than an additive area ( due to the resource sharing), but instead I was surprised to note that Xilinx reported an area larger than (A1 + A2). Whats going on here? Are additional LUT components being used for routing purposes? Im somewhat confused as it did the exact opposite of what I expected. Any help or explanation would be appreciated!


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What exactly did you expect to share ? Think of a state machine as a Set of registers, and a ROM.

The registers that hold the present state, clearly cannot share. The ROMs will individually logic-reduce to pack into logic fabric, but how would sharing help shrink 2 ROMs ?

Suppose a portion of the 2 roms does match, then you will need decoders and MUXs to switch in the shared portion - so you go backwards before you go forwards ( and expect a very smart synthesis tool !)

Then a later state-edit could undo all this....

Generally, you make state-machines smaller by doing the opposite of what you seem to propose : ie sometimes nested machines can be smaller.


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Jim Granville

I wrote the FSM's ina very high level way, to allow the tools to generate their own data path as necessary. Therefore different states may have mulitply operations within them that might be able to share the same multiplier resource, since the two states are disjoint.

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