Hi, I have a design with 2 components, each of which implement a small but non trivial state machine. Each one has an associated area estimate reported by Xilinx, say A1 and A2. Now I realized that both of these components would never execute their state machine concurrently so I combined both state machines into one larger state machine, with the idea that I might be able to save some area since states in both individual state machine might use the same resource. At the very least I thought the new area of the larger state machine would be A1 + A2. I was actually expecting something smaller than an additive area ( due to the resource sharing), but instead I was surprised to note that Xilinx reported an area larger than (A1 + A2). Whats going on here? Are additional LUT components being used for routing purposes? Im somewhat confused as it did the exact opposite of what I expected. Any help or explanation would be appreciated!