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I'm working on a FPGA that is to have a few R/W registers on a VME bus.

Anybody have some VHDL code they would like to share?

If I use your ideas then your name will forever be in lights!


Re: VHDL for FPGA VME Slave
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Be very, very afraid.

VME was defined as an *asynchronous* protocol to keep it
independent of any CPU's clock.  Consequently, any VME
interface needs to be sensitive to EDGES on several different
strobe signals (*DS0, *DS1, *AS and several others).  I think
you can do a reasonable job if you are prepared to oversample
all the strobes with a clock of about 80MHz or faster, but
a direct (asynch) implementation in FPGA would be horrible.

Once you've coped with that asynch-strobes nonsense, the main
remaining problem is performance.  Given that you're only
accessing a few registers, speed may not be a major problem.
If this is so, the rest of the task is comparatively easy -
just a matter of reading the fine print carefully, so that
you don't get confused about address modifiers, word
widths and burst transfers.

Finally, be careful about electrical specs.  VME was defined
around a particular set of LSTTL devices (74LS641-1 bidi
buffers, and a few others).  Output drivers need to be able
to sink 64mA, and be 5V-tolerant, to meet the specs.  74F543
bidi latch/buffer chips are your friends here, if you can
still get 'em.


Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Re: VHDL for FPGA VME Slave
Have a look to :


It seem a well organized job (not mine).

On Fri, 15 Aug 2003, Colin Jackson wrote:

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